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Evaluation of Damages and Pore-sealing Capabilities of Oxidizing and Reducing Etch Plasmas for Single and Dual Damascene Patterning of Porous Ultra-Low-k Materials

Published online by Cambridge University Press:  01 February 2011

Emmanuel Ollier
Affiliation:
emmanuel.ollier@philips.com, Philips Semiconductors, Crolles2Alliance, 860, rue Jean Monnet, Crolles, N/A, 38920, France, (33)4.38.92.21.08, (33)4.38.92.21.20
Mathieu Clain
Affiliation:
mathieu.clain@freescalecrolles.st.com, Freescale Semiconductor, Crolles2Alliance, 870, rue Jean Monnet, Crolles, N/A, 38920, France
Robert Fox
Affiliation:
robert.fox@freescalecrolles.st.com, Freescale Semiconductor, Crolles2Alliance, 870, rue Jean Monnet, Crolles, N/A, 38920, France
Philippe Brun
Affiliation:
philippe.brun-cea@st.com, CEA - LETI, Crolles2Alliance, 17, rue des Martyrs, Grenoble, N/A, 38054, France
Stephane Jullian
Affiliation:
stephane.jullian@philips.com, Philips Semiconductors, Crolles2Alliance, 860, rue Jean Monnet, Crolles, N/A, 38920, France
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Abstract

This paper presents the evaluation of oxidizing and reducing plasmas for post etch pore-sealing treatments during patterning of interconnections in a porous Ultra Low-k (ULK) material. Morphological and chemical characterizations as well as electrical results (resistance, capacitance, leakage, yield) are presented for both single and dual-damascene integrations.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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References

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