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Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps

Published online by Cambridge University Press:  01 February 2011

Hermann Oppermann
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germanyhermann.oppermann@izm.fraunhofer.de; phone: +49 30 46403-163, fax: +49 30 46403-162
Matthias Hutter
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germanyhermann.oppermann@izm.fraunhofer.de; phone: +49 30 46403-163, fax: +49 30 46403-162
Matthias Klein
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germanyhermann.oppermann@izm.fraunhofer.de; phone: +49 30 46403-163, fax: +49 30 46403-162
Gunter Engelmann
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germanyhermann.oppermann@izm.fraunhofer.de; phone: +49 30 46403-163, fax: +49 30 46403-162
Michael Toepper
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germanyhermann.oppermann@izm.fraunhofer.de; phone: +49 30 46403-163, fax: +49 30 46403-162
Jürgen Wolf
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germanyhermann.oppermann@izm.fraunhofer.de; phone: +49 30 46403-163, fax: +49 30 46403-162
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Abstract

Au/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

Type
Research Article
Copyright
Copyright © Materials Research Society 2005

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References

1 Dietrich, L., Engelmann, L., Ehrmann, G., Reichl, O., Gold, H. and Wafer, Gold-Tin Bumping by Electrochemical Deposition for Flip Chip and TAB. 3rd European Conference on Electronic Packaging Technology (EuPac'98), Nuremberg, Germany, June 15-17, 1998.Google Scholar
2 Oppermann, H., Zakel, E., Engelmann, G., Reichl, H.: Investigation of Self-Alignment During Flip-Chip Assembly Using Eutectic Gold-Tin Metallurgy, 4th Int. Conf. and Exhibition on Micro Electro, Opto and Mechanical Systems and Components, MST '94.Google Scholar
3 Kallmayer, Ch., Oppermann, H., Kloeser, J., Zakel, E., Reichl, H., Experimental Results on the Self-Alignment Process Using Au/Sn Metallurgy and on the Growth of the σ-CPhase During the Reflow. Proc. International Flip Chip, Ball Grid Array, TAB and Advanced Packaging Symposium, ITAP'95, San Jose, 1995.Google Scholar
4 Hutter, M., Oppermann, H., Engelmann, G., Wolf, J., Ehrmann, O., Aschenbrenner, R., Reichl, H., Calculation of Shape and Experimental Creation of AuSn Solder Bumps for Flip Chip Applications. Proc 52nd Electronic Components and Technology Conf, San Diego, 2002.Google Scholar
5 Hutter, M., Oppermann, H., Engelmann, G., Wolf, J., Ehrmann, O., Aschenbrenner, R., Reichl, H.: Process Control of the Reflow of AuSn Bumps. Sixth VLSI Packaging Workshop of Japan, November 12-14, 2002, Kyoto Research Park, pp 3942.Google Scholar
6 Hutter, M., Hohnke, F., Oppermann, H., Klein, M., Engelmann, G.: Assembly and Reliability of Flip Chip Solder Joints Using Miniaturized Au/Sn Bumps. Proc. ECTC 54th 2004, Las Vegas, 1-4. June 2004, pp 4957.Google Scholar
7 Schmükle, F.J., Jentzsch, A., Oppermann, H., Riepe, K., Heinrich, W.: W-Band Flip-Chip Interconnects on Thin-Film Substrate. Microwave Symposium Digest, 2002 IEEE MTT-S International, Vol. 3, 2002, pp. 13931396.Google Scholar
8 Chmiel, G., Töpper, M., Jöhren, Ch., Achen, A.: Thinfilm Multichip Modules – Process Development Using Photosensitive BCB. Proceedings of the MST Technologies '94, Berlin, October 1994.Google Scholar
9 Töpper, M.: Entwicklung einer auf Photo-BCB basierenden Technologie für das Waferlevel Packaging. PhD thesis, Technical University Berlin, 2004, Shaker Verlag, ISBN 3-8322-2557-9.Google Scholar
10 Nave, J., Busse, E., Zakel, E., Reichl, H.: TC Bonding for FC-Technology on Ceramic, Silicon and Organic Substrates. ITAP'96, Sunnyvale, CA, Feb. 1996, pp. 9098.Google Scholar
11 Bärwolff, A., Tomm, J.W., Müller, R., Weiβ, S., Hutter, M., Oppermann, H., Reichl, H.: Spectroscopic Measurement of Mounting-Induced Strain in Optoelectronic Devices. IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, May 2000, pp 170175.Google Scholar
12 Elger, G., Hutter, M., Oppermann, H., Aschenbrenner, R., Reichl, H., Jäger, E.: Development of an Assembly Process and Reliability Investigations for Flip-Chip LEDs Using the AuSn Soldering. Microsystem Technologies 7 (2002), Springer-Verlag, pp 239243.Google Scholar
13 Elger, G., Jordan, R., Suchodoletz, M. v., Oppermann, H.: Development of an Low Cost Wafer Level Flip Chip Assembly Process for High Brightness LEDs Using the AuSn Metallurgy. 35th International Symposium on Microelectronics, September 4-6, 2002, Denver, Colorado, pp 199204.Google Scholar
14 Schmückle, F.J., Lenk, F., Hutter, M., Klein, M., Töpper, M., Riepe, K., Heinrich, W., Oppermann, H., Engelmann, G.: W-band Flip-chip VCO in Thinfilm Environment. to be published at 2005 IEEE MTT-S International Microwave Symposium, Long Beach, CA, June 12–17, 2005.Google Scholar