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Microprocessor Architecture
From Simple Pipelines to Chip Multiprocessors

$90.00

textbook
  • Date Published: December 2009
  • availability: Available
  • format: Hardback
  • isbn: 9780521769921

$90.00
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About the Authors
  • This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as – the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers – optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations – design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors – state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

    • Describes how components of a microprocessor work at a black box and algorithmic level often using pseudo-code
    • Has current and historical examples drawn from commercial systems (in side-bars) and research projects
    • Consistently presents topics from conceptual ideas to alternate ways of implementation providing performance metrics whenever possible
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    Reviews & endorsements

    "Professor Baer has developed an extremely appropriate and timely textbook for computer architecture, with a focus on how processors work, and how select micro-architectural features work. He is an excellent teacher, and has effectively presented and explained the concepts. The text covers all the major subjects necessary for a semester-long course in computer architecture."
    Patrick Crowley, Washington University in St. Louis

    "Overall, I believe that the book will serve as a useful textbook for explaining concepts related to the architecture of microprocessors to undergraduate and graduate students."
    S. V. Nagaraj, Computing Reviews

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    Product details

    • Date Published: December 2009
    • format: Hardback
    • isbn: 9780521769921
    • length: 382 pages
    • dimensions: 254 x 178 x 22 mm
    • weight: 0.88kg
    • contains: 104 b/w illus. 20 tables 117 exercises
    • availability: Available
  • Table of Contents

    1. Introduction
    2. The basics
    3. Superscalar processors
    4. Front-end: branch prediction, instruction fetching, and register renaming
    5. Back-end: instruction scheduling, memory access instructions, and clusters
    6. The cache hierarchy
    7. Multiprocessors
    8. Multithreading and (chip) multiprocessors
    9. Current limitations and future challenges.

  • general resources

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    Group Section Name Type Size Sort Order filter vars
    General ResourcesIllustrationsChapter 07pdf49KB0illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 05pdf128KB1illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 04pdf157KB2illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 02pdf117KB3illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 01pdf474KB4illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 08pdf687KB5illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 09pdf19KB6illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 06pdf420KB7illustrations general resources illustrations general resourcesillustrations
    General ResourcesIllustrationsChapter 03pdf202KB8illustrations general resources illustrations general resourcesillustrations
    Instructor ResourcesSolutionsAnswers to Selected Exercisespdf70KB0solutions instructor resources solutions instructor resourcessolutions

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    These resources are provided free of charge by Cambridge University Press with permission of the author of the corresponding work, but are subject to copyright. You are permitted to view, print and download these resources for your own personal use only, provided any copyright lines on the resources are not removed or altered in any way. Any other use, including but not limited to distribution of the resources in modified form, or via electronic or other media, is strictly prohibited unless you have permission from the author of the corresponding work and provided you give appropriate acknowledgement of the source.

    If you are having problems accessing these resources please email cflack@cambridge.org

  • Author

    Jean-Loup Baer, University of Washington
    Jean-Loup Baer is Professor Emeritus of Computer Science and Engineering at the University of Washington, where he has been since 1969. Professor Baer is the author of Computer Systems Architecture and more than 100 refereed papers. He is a Guggenheim Fellow, an ACM Fellow, and an IEEE Fellow. Baer has held several editorial positions, including editor-in-chief of the Journal of VLSI and Computer Systems and editor of the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the Journal of Parallel and Distributed Computing. He has served as General Chair and Program Chair of several conferences, including ISCA and HPCA.

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