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Parallel Computer Organization and Design

$101.00

textbook
  • Date Published: October 2012
  • availability: Temporarily unavailable - no date available
  • format: Hardback
  • isbn: 9780521886758

$101.00
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  • Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software.

    • In-depth coverage of key design issues: complexity, power and reliability, as well as performance
    • Covers core microarchitecture, chip multiprocessors and large-scale multiprocessor systems
    • Contains many examples and end-of-chapter problems, with a solutions manual and lecture slides available online
    Read more

    Reviews & endorsements

    "Parallel computers and multicore architectures are rapidly gaining importance because the performance of a single core is not improving at the same historical level. Professors Dubois, Annavaram, and Stenstrom have created an easily readable book on the intricacies of parallel architecture design that academicians and practitioners alike will find extremely useful." - Shubu Mukherjee, Cavium, Inc.

    "The book can help the readers to understand the principles of parallel systems crystally clear. A necessary book to read for the designers of parallel systems." - Yunji Chen, Institute of Computing Technology, Chinese Academy of Sciences

    "All future electronic systems will comprise of a built-in microprocessor, consequently the importance of Computer Architecture will surge. This book provides an excellent tutorial of Computer Architecture fundamentals from the basic technology via processor and memory architecture to chip multiprocessors. I found the book very educationally flow and readable – an excellent instructive book worth using." - Uri Weiser, Technion

    "This book really fulfils the need to understand the basic technological on-chip features and constraints in connection with their impact on computer architecture design choices. All computing systems students and developers should first master these single and multi core foundations in a platform independent way, as this comprehensive text does." - Mateo Valero, BSC

    "After the drastic shift towards multi-cores that processor architecture has experienced in the past few years, the domain was in dire need of a comprehensive and up-to-date book on the topic. Michel, Murali and Per have crafted an excellent textbook which can serve both as an introduction to multi-core and parallel architectures, as well as a reference for engineers and researchers." - Olivier Temam, INRIA, France

    "Parallel Computer Organization and Design" fills an urgent need for a comprehensive and authoritative yet approachable tutorial and reference text for advanced computer architecture topics. All of the key principles and concepts covered in Wisconsin's three-course computer architecture sequence are addressed in a well-organized, thoughtful, and pedagogically appealing manner, without overwhelming the reader with distracting trivia or an excess of quantitative data. In particular, the coverage of chip multiprocessors in Chapter 8 is fully up to date with the state of the art in industry practice, while the final chapter on quantitative evaluation--a true gem!--is a unique and valuable asset that will clearly set this book apart from its competition." - Mikko Lipasti, University of Wisonsin-Madison

    "The book contains in-depth coverage of all the aspects of the computer systems. It is comprehensive, systematic, and in sync with the latest development in the field. The skillfully organized book uses self-contained chapters to allow the readers get a complete understanding of a topic without wandering through the whole book. Its content is rich, coherent and clear. Its questions are crafted to stimulate creative thinking. I recommend the book as a must read to all graduate students and young researchers and engineers designing the computers." - Lixin Zhang, Institute of Computing Technology, Chinese Academy of Sciences

    "… parallel architectures are the key for high performance and high efficiency computing systems. This book tells the story of parallel architecture at all levels – from the single transistor to the full blown CMP – an unforgettable journey!" - Ronny Ronen, Intel

    "Multicore chips have made parallel architectures ubiquitous and their understanding a necessity. This text provides a comprehensive treatment of parallel system architecture and the fundamentals of cache coherence and memory consistency in the most compact form to date. This is a perfect text for a one semester graduate course." - Lawrence Rauchwerger, Texas A&M University

    "It is the best of today's books on the subject, and I plan to use it in my class. It is an up-to-date picture of parallel computing that is written in a style that is clear and accessible." - Trevor Mudge, Bredt Family Professor of Computer Engineering, The University of Michigan

    "Parallelism, at multiple levels and in many different forms, is now a necessity for all future computer systems, and the new generation of computer scientists and engineers have to master it. To understand the complex interactions among the hundreds of existing ideas, options, and choices, one has to categorize them, put them in order, and then synthesize them. That is precisely what Dubois, Annavaram, and Stenström do, in a magnificent way, in this extremely contemporary and timely book. I want to particularly stress the uniquely clear way in which the authors explain the hardest among these topics: coherence, synchronization, and memory consistency." - Manolis Katevenis, Head of the Computer Architecture and VLSI Systems Laboratory, FORTH-ICS; and Professor of Computer Science, University of Crete, Heraklion, Greece

    "This book is a truly comprehensive treatment of parallel computers, from some of the top experts in the field. Well grounded in technology yet remaining very accessible, it also includes important but often overlooked topics such reliability, power, and simulation." - Norm Jouppi, HP

    "An excellent book in an area that has long cried out for tutorial material --- it will be an indispensable resource to students and educators in parallel computer architecture." - Josep Torrellas, University of Illinois

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    Product details

    • Date Published: October 2012
    • format: Hardback
    • isbn: 9780521886758
    • length: 557 pages
    • dimensions: 252 x 192 x 29 mm
    • weight: 1.3kg
    • contains: 206 b/w illus. 49 tables 95 exercises
    • availability: Temporarily unavailable - no date available
  • Table of Contents

    1. Introduction
    2. Impact of technology
    3. Processor microarchitecture
    4. Memory hierarchies
    5. Multiprocessor systems
    6. Interconnection networks
    7. Coherence, synchronization, and memory consistency
    8. Chip multiprocessors
    9. Quantitative evaluations.

  • instructor resources

    View all resources
    Group Section Name Type Size Sort Order filter vars
    Instructor ResourcesPowerpoint SlidesChapter 8: Chip multiprocessorspptx452KB0powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesPowerpoint SlidesChapter 7: Coherence, synchronisation and memory consistencypptx838KB1powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesPowerpoint SlidesChapter 5: Multiprocessor systemspptx809KB2powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesPowerpoint SlidesChapter 4: Memory hierarchiespptx375KB3powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesPowerpoint SlidesChapter 3: Processor microarchitecturepptx1615KB4powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesPowerpoint SlidesChapter 2: Impact of Technologypptx385KB5powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesPowerpoint SlidesChapter 1: Introductionpptx329KB6powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesPowerpoint SlidesChapter 6: Interconnection networkspptx514KB7powerpoint slides instructor resources powerpoint slides instructor resourcespowerpoint slides
    Instructor ResourcesSolutionsSolutions Manualpdf526KB8solutions instructor resources solutions instructor resourcessolutions

    This title has a locked file and access is given only to instructors adopting the textbook for their class. We need to strictly enforce this so that solutions are not made available to students. To gain access to locked resources you need to first log in with your Cambridge account details and then return to this page to submit details of your course so you can be authenticated as an instructor. Click here to log in. If you do not have a Cambridge account you will first need to click here to create an account and then return to this page to be authenticated.


    These resources are provided free of charge by Cambridge University Press with permission of the author of the corresponding work, but are subject to copyright. You are permitted to view, print and download these resources for your own personal use only, provided any copyright lines on the resources are not removed or altered in any way. Any other use, including but not limited to distribution of the resources in modified form, or via electronic or other media, is strictly prohibited unless you have permission from the author of the corresponding work and provided you give appropriate acknowledgement of the source.

    If you are having problems accessing these resources please email cflack@cambridge.org

  • Instructors have used or reviewed this title for the following courses

    • Advanced Computer Architecture l
    • Advanced Computer Architecture ll
    • Advanced Computer Systems
    • Advanced DSP
    • Advanced Topics in Computer Architecture
    • Architectural Concepts ll
    • Comcurrent and Distrubuted Processing
    • Computer Architecture
    • Computer Architectures
    • Computer Organization
    • Computer Systems Org. & Architecture
    • High Performance Computing for Scientific and Engineering Applications
    • Introduction to Parallel Processing
    • Microprocessor system design
    • Multicore Programming and Architecture
    • Multiprocessor Architecture
    • Parallel Computer Organization
    • Parallel Computer Systems
    • Parallel Computing I
    • Parallel Processing
    • Principles of Computer Architecture
  • Authors

    Michel Dubois, University of Southern California
    Michel Dubois is a Professor in the Ming Hsieh Department of Electrical Engineering at the University of Southern California (USC) and part of the Computer Engineering Directorate. Before joining USC in 1984, he was a research engineer at the Central Research Laboratory of Thomson-CSF in Orsay, France. He has published more than 150 technical papers on computer architecture and edited two books. He is a Fellow of the IEEE and of the ACM.

    Murali Annavaram, University of Southern California
    Murali Annavaram is an Assistant Professor and Robert G. and Mary G. Lane Early Career Chair in the Ming Hsieh Department of Electrical Engineering at the University of Southern California, and part of the Computer Engineering Directorate, where he has developed and taught advanced computer architecture courses. Prior to USC, he spent six years at Intel researching various aspects of future CMP designs.

    Per Stenström, Chalmers University of Technology, Gothenberg
    Per Stenström is a Professor of Computer Engineering at Chalmers University of Technology, Sweden. He has published two textbooks and over 100 technical papers. He has been a visiting scientist at Carnegie-Mellon University, Stanford University and the University of Southern California, and also was engaged in research at Sun Microsystems on its chip-multithreading technology. He is a Fellow of the IEEE and of the ACM and is a member of the Royal Swedish Academy of Engineering Sciences and the Academia Europaea.

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