Designing Digital Computer Systems with Verilog
Adobe eBook Reader
Looking for an evaluation copy?
This title is not currently available for evaluation. However, if you are interested in the title for your course we can consider offering an evaluation copy. To register your interest please contact email@example.com providing details of the course you are teaching.
This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.Read more
- This approach combines tools and methods of VLSI design
- Uses industry-standard Verilog hardware description software
- Complete ground-up approach covers all aspects of a real microprocessor design
Not yet reviewed
Be the first to review
Review was not posted due to profanity×
- Date Published: January 2007
- format: Adobe eBook Reader
- isbn: 9780511261664
- contains: 5 tables
- availability: This ISBN is for an eBook version which is distributed on our behalf by a third party.
Table of Contents
1. Controlling complexity
2. A verilogical place to start
3. Defining the instruction set architecture
4. Algorithmic behavioral modeling
5. Building an assembler for VeSPA
7. Implementation of the pipelined processor
Appendix A: the VeSPA instruction set architecture (ISA)
Appendix B: the VASM assembler
Find resources associated with this titleYour search for '' returned .
Type Name Unlocked * Format Size
*This title has one or more locked files and access is given only to lecturers adopting the textbook for their class. We need to enforce this strictly so that solutions are not made available to students. To gain access to locked resources you either need first to sign in or register for an account.
These resources are provided free of charge by Cambridge University Press with permission of the author of the corresponding work, but are subject to copyright. You are permitted to view, print and download these resources for your own personal use only, provided any copyright lines on the resources are not removed or altered in any way. Any other use, including but not limited to distribution of the resources in modified form, or via electronic or other media, is strictly prohibited unless you have permission from the author of the corresponding work and provided you give appropriate acknowledgement of the source.
If you are having problems accessing these resources please email firstname.lastname@example.org
Sorry, this resource is locked
Please register or sign in to request access. If you are having problems accessing these resources please email email@example.comRegister Sign in
You are now leaving the Cambridge University Press website. Your eBook purchase and download will be completed by our partner www.ebooks.com. Please see the permission section of the www.ebooks.com catalogue page for details of the print & copy limits on our eBooks.Continue ×