Testing of Digital Systems

IDDQ testing refers to detection of defects in integrated circuits through the use of supply current monitoring. This is specially suited to CMOS circuits in which the quiescent supply current is normally very low. Therefore, an abnormally high current indicates the presence of a defect. In order to achieve high quality, it is now well-established that integrated circuits need to be tested with logic, delay as well as IDDQ tests.

In this chapter, we first give an introduction to the types of fault models that IDDQ testing is applicable to, and the advantages and disadvantages of this type of testing. We then present test generation and fault simulation methods for detecting such faults in combinational as well as sequential circuits. We also show how the IDDQ test sets can be compacted.

We look at techniques for IDDQ measurement based fault diagnosis. We derive diagnostic test sets, give methods for diagnosis and evaluate the diagnostic capability of given test sets.

In order to speed up and facilitate IDDQ testing, various built-in current sensor designs have been presented. We look at one of these designs.

We next present some interesting variants of current sensing techniques that hold promise.

Finally, we discuss the economics of IDDQ testing.

Introduction

In the quiescent state, CMOS circuits just draw leakage current. Therefore, if a fault results in a drastic increase in the current drawn by the circuit, it can be detected through the monitoring of the quiescent power supply current, IDDQ.