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6 - IDDQ testing

Published online by Cambridge University Press:  05 June 2012

N. K. Jha
Affiliation:
Princeton University, New Jersey
S. Gupta
Affiliation:
University of Southern California
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Summary

IDDQ testing refers to detection of defects in integrated circuits through the use of supply current monitoring. This is specially suited to CMOS circuits in which the quiescent supply current is normally very low. Therefore, an abnormally high current indicates the presence of a defect. In order to achieve high quality, it is now well-established that integrated circuits need to be tested with logic, delay as well as IDDQ tests.

In this chapter, we first give an introduction to the types of fault models that IDDQ testing is applicable to, and the advantages and disadvantages of this type of testing. We then present test generation and fault simulation methods for detecting such faults in combinational as well as sequential circuits. We also show how the IDDQ test sets can be compacted.

We look at techniques for IDDQ measurement based fault diagnosis. We derive diagnostic test sets, give methods for diagnosis and evaluate the diagnostic capability of given test sets.

In order to speed up and facilitate IDDQ testing, various built-in current sensor designs have been presented. We look at one of these designs.

We next present some interesting variants of current sensing techniques that hold promise.

Finally, we discuss the economics of IDDQ testing.

Introduction

In the quiescent state, CMOS circuits just draw leakage current. Therefore, if a fault results in a drastic increase in the current drawn by the circuit, it can be detected through the monitoring of the quiescent power supply current, IDDQ.

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Publisher: Cambridge University Press
Print publication year: 2003

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  • IDDQ testing
  • N. K. Jha, Princeton University, New Jersey, S. Gupta, University of Southern California
  • Book: Testing of Digital Systems
  • Online publication: 05 June 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9780511816321.007
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  • IDDQ testing
  • N. K. Jha, Princeton University, New Jersey, S. Gupta, University of Southern California
  • Book: Testing of Digital Systems
  • Online publication: 05 June 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9780511816321.007
Available formats
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Save book to Google Drive

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

  • IDDQ testing
  • N. K. Jha, Princeton University, New Jersey, S. Gupta, University of Southern California
  • Book: Testing of Digital Systems
  • Online publication: 05 June 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9780511816321.007
Available formats
×