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Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors

Published online by Cambridge University Press:  11 April 2013

Mustafa B. Akbulut
Affiliation:
Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269
Helena Silva
Affiliation:
Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269
Ali Gokirmak
Affiliation:
Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269
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Abstract

Accumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges.

Type
Articles
Copyright
Copyright © Materials Research Society 2013

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References

REFERENCES

Gokirmak, A. and Tiwari, S., “Accumulated body ultranarrow channel silicon transistor with extreme threshold voltage tunabilityAppl. Phys. Lett., vol. 91, pp. 243504, 2007.CrossRefGoogle Scholar
Asenov, A., Kaya, S. and Brown, A. R., “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” Electron Devices, IEEE Transactions on, vol. 50, pp. 12541260, 2003.CrossRefGoogle Scholar
Baravelli, E., Dixit, A., Rooyackers, R., Jurczak, M., Speciale, N. and De Meyer, K., “Impact of Line-Edge Roughness on FinFET Matching Performance,” Electron Devices, IEEE Transactions on, vol. 54, pp. 24662474, 2007.CrossRefGoogle Scholar
Fan, M. L., Wu, Y. S., Hu, V. P., Hsieh, C. Y., Su, P. and Chuang, C. T., “Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach,” Electron Devices, IEEE Transactions on, vol. 58, pp. 609616, 2011.CrossRefGoogle Scholar
Struck, C. R. M., Neumann, M. J., Raju, R., Bristol, R. L. and Ruzic, D. N., “Grazing incidence ion beams for reducing LER,” in 2008, pp. 71402P.CrossRefGoogle Scholar
Bangsaruntip, S., Cohen, G. M., Majumdar, A., Zhang, Y., Engelmann, S. U., Fuller, N., Gignac, L. M., Mittal, S., Newbury, J. S., Guillorn, M., Barwicz, T., Sekaric, L., Frank, M. M. and Sleight, J. W., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 14.Google Scholar
Synopsys Inc., “Sentaurus TCAD User Manual,” 2011.Google Scholar