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A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatile Memories

  • Moon Kyung Kim (a1), SooDoo Chae (a2), Chung Woo Kim (a3), Jo-won Lee (a4) and Sandip Tiwari (a5)...

The polarity of gates and the threshold voltages are primary parameters that determine the electric fields in the gate stack region of non-volatile memories. This field is central to programming, retention and the other characteristics of the devices. We have investigated the effect of the gate polysilicon polarity, experimentally, for silicon-oxide-nitride-oxide-silicon (SONOS) memory devices on silicon-on-insulator (SOI) wafers. An ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention in our structures. The effect of ONO film, grown and deposited and of doping was simulated and characterized. Retention is affected by the electric field between the control gate and the storage node. Our experiments and simulations verify the consequences of different polarity of control gates through the change in electric field that they cause in retention and erase times for n+ and p+ polysilicon gate SONOS memories is verified through the characteristic energies of the processes.

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  • EISSN: 1946-4274
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