Hostname: page-component-8448b6f56d-xtgtn Total loading time: 0 Render date: 2024-04-24T01:06:04.274Z Has data issue: false hasContentIssue false

A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatile Memories

Published online by Cambridge University Press:  01 February 2011

Moon Kyung Kim
Affiliation:
mkk23@cornell.edu, Cornell University, Electrical and Computer Engineering, 2250N Triphammer RD L3E, Ithaca, NY, 14850, United States, 607-592-2940
SooDoo Chae
Affiliation:
sudu@samsung.com, Samsung Electronics Co., Semiconductor Business, Yongin-City, Kyunggi-Do, N/A, Korea, Republic of
Chung Woo Kim
Affiliation:
cw_kim@samsung.com, Samsung Electronics Co., Semiconductor Business, Yongin-City, Kyunggi-Do, N/A, Korea, Republic of
Jo-won Lee
Affiliation:
jwlee@nanotech.re.kr, Tera-level Nano Devices, Seoul, N/A, Korea, Republic of
Sandip Tiwari
Affiliation:
st222@cornell.edu, Cornell University, Electrical and Computer Engineering, Ithaca, NY, 14850, United States
Get access

Abstract

The polarity of gates and the threshold voltages are primary parameters that determine the electric fields in the gate stack region of non-volatile memories. This field is central to programming, retention and the other characteristics of the devices. We have investigated the effect of the gate polysilicon polarity, experimentally, for silicon-oxide-nitride-oxide-silicon (SONOS) memory devices on silicon-on-insulator (SOI) wafers. An ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention in our structures. The effect of ONO film, grown and deposited and of doping was simulated and characterized. Retention is affected by the electric field between the control gate and the storage node. Our experiments and simulations verify the consequences of different polarity of control gates through the change in electric field that they cause in retention and erase times for n+ and p+ polysilicon gate SONOS memories is verified through the characteristic energies of the processes.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Mielke, N., Fazio, A., and Liou, H., “Reliability comparison of FLOTOX and textured polysilicon EEPROM's,” Proc, Int. Rel. Phys.Symp.,p.85, 1987.Google Scholar
2. Tiwari, S., Rana, F., Hanafi, H., Hartstein, A., Crabbé, E. F., and Chan, K., “A silicon nanocrystals based memory”, Appl. Phys. Lett. 68, 1377, 1996.Google Scholar
3. Libsch, F. R. and White, M. H., “Charge Transport and Storage of Low Programming Voltage SONOS/MONOS Memory Devices,” Solid State Electronics. vol.33, No.1, p.105126, 1990.Google Scholar
4. French, M. L., Chen, C. Y., Sathianathan, H. and White, M. H., “Design and Scaling of a SONOS Multidielectric Device for Nonvolatile Memory Applications,” IEEE Trans. Components, Packaging and Manufacturing Technology, Part A, Vol.17, p390, 1994.Google Scholar
5. Nasyrov, K.A., Kim, Moon Kyung, Chae, H.S., Chae, S.D., Lee, J.-W., and Kim, B.M., “Charge Transport Mechanism in Metal-Nitride-Oxied-Silicon Structures,” IEEE Electron Device Letters, Vol. 23, No.6, p. 336, June 2002.Google Scholar
6. Wann, C. and Hu, C., “High endurance ultra-thin tunnel oxide for dynamic memory application,” Tech. Dig of IEDM, p.867870, 1995.Google Scholar