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A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)

Published online by Cambridge University Press:  15 February 2011

Jeffrey A. Davis ,
John C. Eble ,
Vivek K. De  and
James D. Meindl
Jeffrey A. Davis
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, gt4020c@prism.gatech.edu
John C. Eble
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, gt4020c@prism.gatech.edu
Vivek K. De
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, gt4020c@prism.gatech.edu
James D. Meindl
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, gt4020c@prism.gatech.edu
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Abstract

Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASIC's over the next 15 years.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 427: Symposium K – Advanced Metallization for Future ULSI , 1996 , 23
Copyright
Copyright © Materials Research Society 1996

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