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Electrical Characterization of Copper Penetration Effects in the Gate Oxide of MOS Devices

Published online by Cambridge University Press:  17 March 2011

François Mondon ,
Jacques Cluzel ,
Denis Blachier ,
Yves Morand ,
Laurent Martel  and
Gilles Reimbold
François Mondon
Affiliation:
LETI (CEA-Grenoble), 38054 Grenoble-Cedex 9, France J. FourierUniversity-Grenoble, France, fmondon@cea.fr
Jacques Cluzel
Affiliation:
LETI (CEA-Grenoble), 38054 Grenoble-Cedex 9, France
Denis Blachier
Affiliation:
LETI (CEA-Grenoble), 38054 Grenoble-Cedex 9, France
Yves Morand
Affiliation:
ST Microelectronics, 38926 Crolles cedex, France
Laurent Martel
Affiliation:
LETI (CEA-Grenoble), 38054 Grenoble-Cedex 9, France
Gilles Reimbold
Affiliation:
LETI (CEA-Grenoble), 38054 Grenoble-Cedex 9, France
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Abstract

Copper penetration in thermal oxide was investigated using MOS capacitors by annealing at 450 °C and bias-temperature stress at 250 °C. Copper induces minority carrier generation lifetime decay and oxide leakage current increase. Degradation is enhanced by capacitor biasing, which confirms the role of Cu+ ions. The current-voltage characteristics are consistent with Poole-Frenkel model, showing that electron transport proceeds through traps created in the oxide bulk by copper. When a negative bias is applied, copper traps are removed from oxide near SiO2-Si interface and the leakage current is cancelled but the generation lifetime remains nil, copper contamination of silicon surface being not removed.

None of these effects are observed when the copper gate is separated from oxide by a 10 nm TiN layer, proving that this material is an efficient barrier against copper diffusion at 450°C.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 714: Symposium – Materials, Technology and Reliability for Advanced Interconnects and Low-k Dielectrics II , 2001 , L8.12.1
Copyright
Copyright © Materials Research Society 2001

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References

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