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Low Temperature Selected Area Re-Growth of Ohmic Contacts for III-N FETs

  • Yoganand Saripalli (a1), Chang Zeng (a2), Yawei Jin (a3), Joseph P Long (a4), Judith A Grenko (a5), Krishnanshu Dandu (a6), Mark A.L Johnson (a7) and Doug W Barlage (a8)...

GaN has a wide band gap energy, high electron mobility, high saturation velocity, and excellent thermal properties making it a promising material for high power and high frequency electronic devices. The development of enhancement mode GaN metal oxide semiconductor (MOS) transistors has been elusive due to the non-availability of a good insulating gate dielectric and the difficulty in forming of ohmic source/drain regions. Ion-implantation of dopants causes severe lattice damage requiring a high temperature post-implant anneal and has not been a successful method to obtain acceptable low-resistance source/drain regions. At the same time, gate dielectrics for most compound semiconductors, in addition to difficulties in minimizing the density of interface states which pin the Fermi level by inducing trap levels in the midgap, are degraded by instabilities as a result of high temperature annealing. The paper presents the development ohmic source/drain contacts for GaN MOSFETs by selected area epitaxial regrowth. Re-growth of GaN on patterned substrates by metal-organic chemical vapor deposition (MOCVD) employs a growth regime to decrease the enhanced growth rates and island formation that result from the diffusion of precursors to the selected area. The enhanced growth rate is 4.5μm/hr compared to 0.5μm/hr of the as-grown GaN on the unpatterned substrate. The enhanced growth rate also results in heavily porous GaN. Selected area growth, device processing, the material and device characterization results will be presented. In particular the selected area growth of doped contacts in the 800°C temperature range leads to superior morphology and contact resistance as compared to similar contacts grown at 1060°C. The contact resistivity of the n+ re-growth region measured was ∼2×10-4 Ω-m and the morphology of the re-grown region was comparable to the as-grown GaN with an RMS roughness ∼1.4nm. The success of fabricating low temperature contacts for GaN enhancement mode MOS transistors is a critical step in fabricating these devices opening new applications.

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