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Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

  • Shi-Wei Ricky Lee (a1) and Ronald Hon (a2)

The study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

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1. Hon, R. and Lee, S. W. R., “Design, Process Development and Prototyping of 3D Packaging with Multi-Stacked Flip Chips and Peripheral Through Silicon Via Interconnection,” Proc. 31st International Conference on Electronics Manufacturing and Technology, Malaysia, November 8–10, 2006, pp. 8085.
2. Hon, R., Lee, S. W. R., Zhang, X. D. and Wong, C. K., “Multi-Stack Flip Chip 3D Packaging with Copper Plated Through Silicon Vertical Interconnection,” Proc. 7th Electronic Packaging Technology Conference, Singapore, December 7–9, 2005, pp. 384389.
3. Lee, S. W. R., Hon, R., Zhang, X. D. and Wong, C. K., “3D Stacked Flip Chip Packaging with Through Silicon Vias and Copper Plating or Conductive Adhesive Filling,” Proc. 55th Electronic Components & Technology Conference, Florida, May 31- June 3, 2005, pp. 795801.
4. Lee, S. W. R., Hon, R. and Zhang, X. D., “Formation of Through-Silicon-Vias by Laser Drilling and Deep Reactive Ion Etching,” Proc. 16th Symposium on Mechanics of SMT & Photonic Structures, ASME International Mechanical Engineering Congress & Exposition, Anaheim, California, U.S.A., November 1320, 2004. (IMECE2004/62322 on CD-ROM)
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6. Spiesshoefer, S. and Schaper, L., “IC Stacking Technology Using Fine Pitch, Nanoscale Through Silicon Vias,” Proc. 53rd Electronic Components & Technology Conference, New Orleans, LA, May 27–30, 2003, pp. 631633.
7. Wang, L., Nichelatti, A., Schellevis, H., de Boer, C., Visser, C., Nguyen, N. T. and Sarro, P. M., “High Aspect Ratio Through-Wafer Interconnections for 3D-Microsystems,” Proc. 16th IEEE International Conference on MEMS, Kyoto, Japan, January 19–23, 2003, pp. 634637.
8. Yeom, J., Wu, Y., and Shannon, M. A., “Critical Aspect Ratio Dependence in Deep Reactive Ion Etching of Silicon,” Proc. 12th International Conference on Transducers, Solid-State Sensors, Actuators & Microsystems, June 8–12, 2003, pp. 16311634.
9. Nguyen, N. T., Boellaard, E., Pham, N. P., Kutchoukov, V. G., Craciun, G. and Sarro, P. M., “Through-Wafer Copper Electroplating for Three-Dimensional Interconnects,Journal of Micromechanics & Microengineering, 2002 (12), pp. 395399.
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