Hostname: page-component-7c8c6479df-27gpq Total loading time: 0 Render date: 2024-03-27T03:36:37.442Z Has data issue: false hasContentIssue false

Self-Aligned, Metal-Masked Dry Etch Processing of III-V Electronic and Photonic Devices

Published online by Cambridge University Press:  25 February 2011

S. J. Pearton
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ
A. Katz
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ
A. Feingold
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ
F. Ren
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ
T. R. Fullowan
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ
J. R. Lothian
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ
C. R. Abernathy
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ
Get access

Abstract

Electron Cyclotron Resonance (ECR) plasma etching of a variety of III-V devices, including heterojunction bipolar transistors (HBTs), and lasers will be reviewed. In many of these devices, the metal contacts also perform as self-aligned, dry etch masks, so that mask erosion must be addressed. Sidewall smoothness is also an issue for most etched mesa lasers, and conditions for achieving the requisite smoothness will be discussed. The use of stencil masks for pattern transfer of large (∼100μm) features during cluster-tool, single wafer integrated processing raises the possibility of a completely in-situ fabrication technology without the need for lithography. The dry etching of a variety of ohmic and Schottky metallizations and also of dielectrics deposited in a low pressure, rapid thermal CVD system lays the foundation for integrated III-V device processing.

Type
Research Article
Copyright
Copyright © Materials Research Society 1992

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Pearton, S. J., Ren, F., Abernathy, C. R., Fullowan, T. R. and Lothian, J. R., Semicond. Sci. Techn. 6 1116(1991).Google Scholar
2. Constantine, C., Johnson, D., Pearton, S. J., Chakrabarti, U. K., Emerson, A. B., Hobson, W. S. and Kinsella, A. P., J. Vac. Sci. Technol. B5 596 (1990).Google Scholar
3. Asmussen, J., J. Vac. Sci. Technol. A7 883 (1989).Google Scholar
4. Chakrabarti, U. K., Pearton, S. J. and Ren, F., Semicond. Sci. Techn. 6 408 (1991).Google Scholar
5. Burton, R. H., Gottscho, R. A. and Smolinsky, G. in Dry Etching for Microelectronics, ed. Powell, K. A. (Elsevier, NY 1984) p. 79.CrossRefGoogle Scholar
6. Flamm, D. L., in Plasma Etching - An Introduction, ed. Manos, D. M. and Flamm, D. L. (Academic Press, NY 1989) p. 53.Google Scholar
7. Pearton, S. J., Mat. Sci. Eng. B10 187 (1991).Google Scholar
8. Ren, F., Fullowan, T. R., Abemathy, C. R., Pearton, S. J., Smith, P., Kopf, R. F., Laskowski, E. J. and Lothian, J. R., Electron. Lett. 27, 1054 (1991).CrossRefGoogle Scholar
9. Ren, F., Abemathy, C. R., Pearton, S. J., Fullowan, T. R., Lothian, J. R., Wisk, P. W., Chen, Y. K., Hobson, W. S. and Smith, P., Electron Lett. 27 2391 (1991).Google Scholar
10. Kim, M. E., Oki, A. K., Gouman, G. M., Umemoto, D. K. and Camov, J., IEEE Trans. MTT 37 1286 (1989).Google Scholar
11. Fullowan, T. R., Pearton, S. J., Kopf, R. F. and Smith, P. R., J. Vac. Sci. Technol. B9 1445 (1991).Google Scholar
12. Fullowan, T. R., Pearton, S. J., Kopf, R. F., Chen, Y. K., Chin, M. A. and Ren, F., Electron. Lett. 27 2340 (1991).Google Scholar
13. Pearton, S. J., Corbett, J. W. and Shi, T. S., Appl. Phys. A43 153 (1987).Google Scholar
14. Katz, A., Pearton, S. J. and Geva, M., J. Appl. Phys. 65 3110 (1990).Google Scholar
15. Katz, A., Pearton, S. J. and Geva, M., Appl. Phys. Lett. 59 286 (1991).CrossRefGoogle Scholar
16. Karlicek, R. F. Jr, Katz, A., Logan, R. A., Pearton, S. J., Van der Ziel, J. P., Sergent, A. M. and Ha, N. T. (unpublished).Google Scholar
17. Katz, A., Feingold, A. and Pearton, S. J., Semicond. Sci. Technol. 7 436 (1992).Google Scholar