Hostname: page-component-7c8c6479df-xxrs7 Total loading time: 0 Render date: 2024-03-28T21:51:36.103Z Has data issue: false hasContentIssue false

Stressmigration studies on dual damascene Cu/oxide and Cu/low k interconnects

Published online by Cambridge University Press:  17 March 2011

Won-Chong Baek
Affiliation:
Microelectronics Research Center, the University of Texas at Austin, Austin, TX 78712, USA
Paul. S. Ho
Affiliation:
Microelectronics Research Center, the University of Texas at Austin, Austin, TX 78712, USA
Jeong Gun Lee
Affiliation:
System IC R&D Center, Hynix Semiconductor Inc., 1 Hyangjeong-dong, Hungduk-gu, Cheongju Si, 361-725, South Korea
Sung Bo Hwang
Affiliation:
System IC R&D Center, Hynix Semiconductor Inc., 1 Hyangjeong-dong, Hungduk-gu, Cheongju Si, 361-725, South Korea
Kyeong-Keun Choi
Affiliation:
System IC R&D Center, Hynix Semiconductor Inc., 1 Hyangjeong-dong, Hungduk-gu, Cheongju Si, 361-725, South Korea
Jong Sun Maeng
Affiliation:
System IC R&D Center, Hynix Semiconductor Inc., 1 Hyangjeong-dong, Hungduk-gu, Cheongju Si, 361-725, South Korea
Get access

Abstract

Stress-induced void formation (SIV) was studied in dual damascene Cu/oxide and Cu/low k interconnects over a temperature range of 140 ∼ 350 °C. Two modes of stressmigration were observed depending on the baking temperature and sample geometry. At lower temperatures (T < 290 °C), voids were formed under the periphery of via connecting to narrow lines. This mode of stressmigration showed a typical behavior of stressmigration with peak damage at 240 °C, and an activation energy (Q) of 0.75 eV for Cu/oxide interconnects. At a higher temperature range (T > 290 °C), voids were found in via bottoms which were connected to wide lines. The rate of high temperature stressmigration increased exponentially with temperature up to 350 °C and did not show a peak at a certain temperature. The activation energy was 1.0 eV for Cu/oxide, 0.86 eV for Cu/OSG, and ∼1.0 eV for Cu/FSG interconnects. The dependence of stressmigration on linewidth, sample geometry, and ILD material is presented in this paper.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Okabayashi, H. et al. , Mat. Sci. & Eng. R11, No 5, 189 (1993).Google Scholar
2. Ogawa, E. T. et al. , “Stress-induced voiding under vias connected to wide Cu metal leads”, Proc. IRPS (2002)Google Scholar
3. Matsumoto, S. et al. , “Reliability Improvement of 90 nm-node Cu/Low-k interconnects”, Proc. IITC (2003)Google Scholar
4. Hu, C.-K. et al. , IBM J. Res. Devlop. Vol. 39 No. 4, 465 (1995)Google Scholar
5. McPherson, J. W. et al. , J. Vac. Sci & Tech. B5(5), 1321 (1987)Google Scholar
6. Lee, K. et al. , Appl. Phy. Let., Vol. 79, No., 3236 (2001)CrossRefGoogle Scholar
7. Glascow, A. von et al. , Proc. “New approaches for the assessment of stress-induced voiding in Cu interconnects”, IITC (2002)Google Scholar
8. Ogawa, E. T. et al. , IEEE Trans. Rel., vol. 51, No. 4, 403 (2002)CrossRefGoogle Scholar