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Threshold Voltage Performance of a-Si:H TFTs for Analog Applications

Published online by Cambridge University Press:  01 February 2011

K.S. Karim ,
K. Sakariya  and
A. Nathan
K.S. Karim
Affiliation:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1Canada.
K. Sakariya
Affiliation:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1Canada.
A. Nathan
Affiliation:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1Canada.
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Abstract

Amorphous silicon (a-Si:H) thin-film transistors (TFT) used in emerging, non-switch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (VT) stability performance. At small gate voltages (0 ≤ VST ≤ 15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain is found to decrease the shift in VT (ΔVT) compared to the ΔVT in the absence of a drain bias. In this paper, a ΔVT model accounting for TFT drain bias, is used to predict the performance of a-Si:H analog circuits in active pixel sensor (APS) medical xray imaging and active matrix, organic light emitting diode (AMOLED) display applications.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 762: Symposium A – Amorphous and Nanocrystalline Silicon-Based Films – 2003 , 2003 , A20.4
Copyright
Copyright © Materials Research Society 2003

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