Preliminary theoretical models for the electronic structure of grain boundaries and interfaces in polycrystalline ZnO have been constructed on the basis of self-consistent-field X-alpha scattered-wave (SCF-Xα-SW) cluster molecular-orbital calculations. The disposition and character of the interface states, relative to the valence and conduction bands of the otherwise perfect crystalline material, have been studied for clusters representing coordinatively unsaturated Zn surface sites and molecular O2 chemisorption thereon. The possible effects of the resuiting interface states on electron transport at grain boundaries in ZnO varistors have been addressed.

The molecular character of arsenic adsorbed on the Si (100) surface has been investigated using thermal desorption spectroscopy (TDS) and Auger electron spectroscopy (AES). A variety of arsenic surface species were deposited on the silicon surface by employing different evaporation sources, including metallic arsenic, arsine gas, and chips of GaAs crystals. We present coverage dependent spectra showing the desorption of As4 tetramers at 350°C and As2 dimers at 900°C. The loosely bound arsenic is adsorbed from the solid evaporation sources only and resides on the surface as tetramers. The tightly bound arsenic does not form multiple layers and the high desorption temperatures suggests the adsorbed arsenic exists as monomers.

The method of preparation of polycrystalline silicon can have a strong influence on the types and distributions of grain boundaries, and thereby influence the electrical properties of devices made from such materials. Examples of methods employed in the preparation of polycrystalline silicon for solar cell applications include directional solidification (Czochralski pulling and various casting techniques), ribbon growth techniques (ribbon-to-ribbon, edgedefined film-fed growth, low-angle silicon sheet growth, edge supported pulling, silicon-on-ceramic), chemical and physical vapor deposition (CVD and PVD) on silicon and foreign substrates, recrystallization techniques (laser, electron beam), and others such as graphoepitaxy and electrodeposition. This paper reviews the important morphological features such as grain size and defect structures of the various polycrystalline silicon materials and the influence of growth parameters on these features. The effects of grain boundaries on the electrical and photovoltaic properties of various polycrystalline silicon materials will also be discussed.

Two examples are given of the application of EBIC and HVTEM to the study of defects in silicon.

An hexagonal dislocation network in a coherent first order twin boundary in WEB silicon shows a three fold symmetry when imaged by EBIC. The observed variation of the minority carrier lifetime at the nodes is consistent with a model which assumes that jogs are particularly strong recombination sites at a dislocation.

EBIC and STEM observations on unprocessed and processed EFG ribbon show that the phosphorus diffused junction depth is not uniform, and that a variety of chemical impurities precipitate out during processing. Two kinds of precipitates are found i) 10 nm or less in size, located at the dislocation nodes in sub-boundary like dislocation arrangements formed during processing and ii) large precipitates, the chemical composition of which has been partially identified. These large precipitates emit dense dislocations tangles into the adjacent crystal volume.

An enhanced photoresponse at dislocation subgrain boundaries (in comparison with grain boundaries and dislocation-associated twin boundaries) is attributed to an increased junction depth at their positions relative to the value of the minority carrier diffusion length, Ln. For reasonably pure material, Ln is determined by the dislocation density. The dislocation microstructure of polysilicon solar cells is advantageously studied by means of the several x-ray topography techniques.

The effects of heat treatment at temperatures appropriate for solar cell device fabrication on grain boundaries in cast poicrystalline silicon have been studied. An MIS device structure using a 200° C heating was used for fabricating test devices on heat treated samples for EBIC studies. Grain boundary effective surface recombination velocities (Seffgb ) and effective mid-grain diffusion lengths were measured. Seffgb was found to increase after heat treatment. Segregation of oxygen to grain boundaries has been observed in heat treated samples.

The effect on the diode characteristics when a conducting grain boundary intersects a pn junction is analyzed. The possibilities of conducting grain boundaries are related to the levels associated with precipitates at the grain boundary. The effect of the grain boundary on the diode characteristics is found particularly degrading when donor impurities precipitate in the n region while simultaneously acceptor impurities precipitate in the p region. Both solar cell characteristics and the dark diode characteristics are analyzed.

MS and MIS solar cell performance as a function of wet chemical etching history has been studied and correlated with lattice strain obtained from x-ray double-crystal diffraction technique and intragranular surface topography. Dry ion beam etching from a Kaufman ion source is found to damage the surface and radically alter the electrical barrier by introducing donor-like states in the damaged region.

Many problems exist in current attempts to develop polycrystalline GaAs as a basis for thin-film solar cells. Some of these problems arise from the direct interaction of carriers, both dark and photo-generated, with grain boundaries. Others are more indirect; e.g., shunting currents due to the grain boundary-enhanced diffusion of contaminating impurities. This paper describes several of these effects, including the influence of system chemistry on grain properties, the correlation of device parameters with grain size, and grain boundary passivation experiments. A review of various approaches to solving the problems confronting the field is given, and an attempt is made to interpret reported observations in terms of existing theoretical models.

A technique for making rapidly-scanned, high-spatial resolution measurements of minority-carrier diffusion length is applied to the characterization of polycrystalline GaAs. Measurements on a large-grained n-type epitaxial layer show gradual variations of hole diffusion length from 0.1µm to l.lµm across the wafer as well as occasional small step changes at grain boundaries. By trading resolution for speed, the technique would be well suited to the nondestructive evaluation of large-area epitaxial layers.

N–type Ga-As polycrystalline layers, grown on Mo substrates by the metal-organic process were investigated using the SEM. Micrographs of charge collection contrast indicate a fairly random distribution of high collection (bright) grains. In a typical cell about 1/3 of its area is bright, with nonuniformities in collection current within and between grains. These results correlate well with Isc measurements, and some of the variations betweencells is explained in terms of insufficient doping of the grain boundaries.

Reducing the penetrating depth of the carriers' excitation volume results in lowering of the collection current. The measurements were normalized for changes in beam and EBIC current by a comparison with a single crystal cell of the same geometry. This degradation is explained in terms of contamination or damage of the layer close to the surface during growth.

Grain boundaries in Wacker poly-Si are shown to contribute mid-gap interface states, a greater frequency dependence in a.c. conductance, and lesser frequency dependence in capacitance. H-passivation was shown to be effective in reducing grain boundary effects as evidenced by 4-point probe resistance and IR studies.

Wacker polycrystalline silicon shows enhanced grain boundary activity after a high temperature (950° C) anneal. It is possible to passivate this effect in a hydrogen plasma. The low temperature (600° C) processing of MIS technology does not activate grain boundaries or deteriorate a passivated specimen. Activated grain boundaries with MIS structures can be used to assess the character of recombination currents. It is concluded that MIS processing is advantageous for passivated polycrystalline silicon.

A new method for making p-n junctions based on immersion in a transparent dopant gas followed by irradiation with a pulsed laser is presented. The surface of the wafer melts, dopant from the gas dissolves in it, and is distributed by liquid diffusion before epitaxial regrowth. This technique, termed GILD for Gas Immersion Laser Diffusion, was used to make solar cells in both monocrystalline and polycrystalline silicon.

Laser photocurrent scanning shows that grain boundary recombination is reduced or eliminated in cells made by the GILD technique and current collection is enhanced at some grain boundaries. Heat treatment at 850 ° C prior to GILD causes the same grain boundaries to be recombination active as they are in ordinary diffused cells.

Poly-crystalline silicon can be regarded as a true electronic material if good p-n junctions can be made in it or if its state of depletion can be altered by reasonable gate voltages. The degree of perfection with which it must exhibit these electronic-material properties depends on whether the application is as a technology in VLSI (or other bulk-Si substrate use) where devices with bulk-crystalline properties are available or as the principal active material in Large Area Integration (LAI), such as flat-panel display addressing circuits, where the competition is much less demanding. The three main detrimental effects of grain boundaries on electronic-device function are the action of grain boundary traps as (1) extra charge centers, (2) lifetime killers, and (3) mobility-reducing scattering centers. The current trend in reducing or almost eliminating grain boundaries by laser recrystallization or lateral epitaxy has the effect of reducing the average number of traps. In terms of potential applications of the material, the improvement derived from these procedures must be balanced against other contraints placed on the overall structure. For example, the thickness and quality of the lower oxide (and interface) in these processes will determine whether an electronically active lower gate function is practical. Some currently envisioned applications include load devices in inverters either as resistors or as depletion transistors, common-gate staked CMOS structures, dual-channel MOSFET's, and other “vertical VLSI” applications. The systems-level topological advantages of stacked structures and the circuit-performance improvement provided by the ground plane in dielectrically isolated devices must also be balanced against the extra cost and yield loss of additional masking level complexity and design complication.

Physical and electrical properties of chemically-vapordeposited polycrystalline silicon films have been investigated. Effects of deposition parameters, doping, and high temperature processing on grain size and orientation, carrier concentration, carrier mobility and electrical resistivity, have been studied. By relating the physical and electrical properties to each other it has been shown that electrical conduction is controlled by dopant segregation, carrier tunneling, and trapping at grain boundaries. Models for these three mechanisms have been developed and by combining them a generalized model for electrical conduction has been developed. Presence of grain boundaries has also been shown to strongly influence the thermal oxidation and dopant diffusion in polycrystalline silicon.

Surface mobilities in laser-processed polysilicon films were measured using silicon-gate n-channel thin-film transistors of varying dimensions. The apparent surface mobility inferred from transconductance measurements was found to be a decreasing function of channel length. For very short (~0.3/µm) channels, this mobility approaches the surface mobility of identical devices fabricated on bulk silicon. Furthermore, the temperature dependence of the surface mobilities in polycrystalline and bulk films was found to be identical.

A novel EBIC technique was employed to examine the surface potential of transistors in operation. These measurements indicate a high degree of spatial nonuniformity in the inversion layer of polycrystalline films arising from the grain boundary region. A simple model of the transistors is presented which explains the geometry dependent surface mobility and its temperature dependence.

The presence of residual grain boundaries in laser-crystallized thin films of silicon necessitates an understanding of their properties and effects on device operation. In CW laser crystallized silicon islands, lateral p-n junction diodes have been used to evaluate the following: (1) enhanced arsenic diffusion along grain boundaries, (2) current-voltage characteristics, and (3) effects of hydrogenation on diode operation. To study the process of hydrogen passivation, deuterium has been used as a readily identifiable isotope which duplicates hydrogen chemistry. From secondary-ion mass spectrometry, diffusion of deuterium in single-crystal and polycrystalline silicon at low temperatures (e.g., 350 C) clearly demonstrates that grain-boundary diffusion dominates bulk diffusion.

The operation of a MOSFET transistor fabricated in undoped, small-grain polysilicon is considered, and a model is developed which can predict threshold and drain current as a function of gate voltage. A two-dimensional calculation is described for the band-bending under the influence of a gate potential with the assumption that the grain boundaries are repetitive and oriented at right angles to the gate-oxide/polysilicon interface. Both hole and electron traps are assumed present at the grain boundaries and are coincident in energy with the intrinsic Fermi level at room temperature. An energy barrier to the flow of carriers is present in the undoped polysilicon, and the magnitude of this energy barrier is dependent on the gate voltage. The band-bending occurs over much shorter distances than the intrinsic Debye length, and the trapped charge at the grain boundaries behaves very similarly to the charged impurities in a depletion model. The two-dimensional model can be approximated by a one-dimensional calculation for the band-bending by making the assumption that the trapped charge is uniformly distributed throughout the grain. The results of this calculation can be used to calculate the magnitude of the free carriers in the channel region. Using this information, the dependence of the potential barrier on gate voltage, and the gradual channel approximation for an FET, one can compute the drain current vs. gate voltage, and the results of these calculations are given for parameters used in fabricating actual devices. Finally, experimental results are compared with the model for typical transistors fabricated in undoped, small-grain polysilicon.

Grain boundary diffusion of arsenic and phosphorus in laser processed polycrystalline Si films has been investigated. Mesa diodes were fabricated in LPCVD Si thin films on SiO2 and subsequently recrystallized by cw Ar ion laser processing to form large grain material. The diffusion length of enhanced As and P diffusion along grain boundaries intersecting the p-n junction has been measured by the EBIC technique. Quantitative experimentation allowed determination of the grain boundary diffusion coefficients of As and P in the temperature range from 900°C to 1250°C.