Polysilicon based Thin Film Transistors (poly-Si TFT's) with superior electrical performance can be achieved by maximizing the number of intrinsic point defect injected into the material during high temperature processing. These point defects will migrate to grain boundaries (GB's), enhance their mobility by facilitating climb, and allow the boundary to achieve a low energy configuration with a minimum of electrically active broken bonds. Proper processing of poly-Si TFT's therefore requires a redesign of the conventional processing cycle where, working with single crystal silicon, one minimizes the concentration of intrinsic point defects which otherwise precipitate out as Oxidation induced Stacking Faults (OSF's).

TFT's were fabricated under nine different processing cycles to study the relationship between device performance and fabrication conditions. Device performance increased with higher gate oxidation temperature, elimination of HCI flow during gate oxidation, post hydrogenation, and multiple gates. Using conventional MOS processing steps only, n-type (p-type) devices were fabricated, which were capable of handling 40 volts VDS with a leakage current of 2×10−11 (6×10−12) A/μm and effective electron (hole) channel mobilities of 130 (50) cm2/Vs.

The lifetime of optically injected carriers is determined in polySi/SiO2/Si structures grown by LPCVD at 625°C. These samples are as-grown, have undergone H diffusion or have been implanted by phosphorous ions, followed by various annealing schedules. The lifetime measurement is done in an all-optical, contactless fashion, using the tools of picosecond time-resolved spectroscopy. We find that the lifetime due to recombination at the grain boundaries (trapping time) increases after implantation only if subsequent annealing increases the grain size. The trapping time also increases after hydrogen diffusion. After trapping in relatively shallow grain boundary states, thermalization into deeper lying states is slow on a subnanosecond time scale.

Poly-Si films were e-gun evaporated onto glass substrates. The Hall-mobility for holes was found to be about 2 cm2/Vs in undoped poly-Si films deposited at 400°C and 9 cm2/Vs at 500°C. TFTs were fabricated on the base of poly-Si evaporation technique on borosilicate glass at a highest process temperature of 550°C without ion implantation. The electrical TFT characteristics yield electron field-effect mobilities higher than 10 cm2/Vs as well as threshold voltages less than IV and an on/off current ratio in excess of 104.

We studied the crystallization of LPCVD amorphous silicon films by TEM and found that the grain size of crystallized films depends upon the deposition and annealing conditions. The grain size increases as the deposition and/or the annealing temperature decreases. We also investigated the application of crystallized films in the fabrication of polysilicon emitter bipolar transistors and thin film transistors. The performance of bipolar transistors was found to have a small dependence on the grain size. In contrast, the performance of thin film transistors was strongly dependent upon the grain size.

Diffusion of arsenic implanted in poly-silicon on insulator structures after furnace and rapid thermal annealing (RTA) has been investigated by Rutherford backscattering (RBS) and Hall effect measurements. The diffusivity for As in poly–Si on insulator is represented by D = 3.12 × 104 exp (− 3.86/kT) cm/sec for the tail region after both RTA and furnace annealing and D = 34.0 exp (− 3.42/kT) cm2/sec for the peak region after RTA. Poly–Si layers after implantation and annealing were found to have tensile stresses of 3.0 – 4.0 kbar.

Low temperature, 600°C annealing of LPCVD films was investigated by x-ray diffraction, ESR, TEM, and carrier mobility measurements. An optimum deposition temperature of about 550°C was found to yield good crystallinity and large electron mobility for annealed films; large grain sizes, a maximum crystallite size, and a maximum electron spin density were also observed for films deposited at the optimum temperature. Electron spin density for as-deposited films correlated with the crystalline volume by x-ray diffraction measurements on the films after annealing. This implys that only those amorphous components with high electron spin density can be converted into the crystalline phase by 600°C annealing.

We have carried out transient photoconductivity experiments on hydrogenated and unhydrogenated polysilicon Thin Film Transistors (TFTs) which indicate that the primary effect of plasma hydrogenation is the reduction by several orders of magnitude of the band tail trapping states. A smaller effect is a reduction of the dangling bond density by a factor of 2 or 3 as indicated by Electron Spin Resonance (ESR) measurements. Since the dangling bond is associated with the generation/recombination center, it may not be obvious how such a small reduction in generation/recombination center density leads to over 2 orders of magnitude reduction in off-state current of the TFTs. In this paper, we describe how the large reduction of band tail states can lead to significant reduction of carrier generation near the contacts despite the fact that the generation/recombination center density is not changed significantly. This reduction of carrier generation leads to the observed reduction in off-state currents.

Grain boundary properties of polysilicon deposited by molecular beams have been investigated by electron spin resonance and conductivity measurements. The variations of the conductivity activation energy with doping can be explained by a density of states model consisting mainly of two exponential bandtails, implying that dangling bonds play a minor role. A hydrogen plasma treatment at 500 °C reduces the spin density by a factor of three but also passivates weak Si-Si bonds thus leading to steeper bandtails. The possibility of hydrogen-related intra-grain gap states is also discussed.