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7 kV 4H-SiC GTO Thyristors

Published online by Cambridge University Press:  11 February 2011

Stephen Van Campen ,
Andris Ezis ,
John Zingaro ,
Garrett Storaska ,
R. Chris Clarke ,
Vic Temple ,
Mark Thompson  and
Todd Hansen
Stephen Van Campen
Affiliation:
Northrop Grumman, Advanced Materials and Semiconductor Device Technology Center, PO Box 1521 MS 3B10, Baltimore, MD 21203
Andris Ezis
Affiliation:
Northrop Grumman, Advanced Materials and Semiconductor Device Technology Center, PO Box 1521 MS 3B10, Baltimore, MD 21203
John Zingaro
Affiliation:
Northrop Grumman, Advanced Materials and Semiconductor Device Technology Center, PO Box 1521 MS 3B10, Baltimore, MD 21203
Garrett Storaska
Affiliation:
Northrop Grumman, Advanced Materials and Semiconductor Device Technology Center, PO Box 1521 MS 3B10, Baltimore, MD 21203
R. Chris Clarke
Affiliation:
Northrop Grumman, Advanced Materials and Semiconductor Device Technology Center, PO Box 1521 MS 3B10, Baltimore, MD 21203
Vic Temple
Affiliation:
Silicon Power Corporation, 175 Great Valley Parkway, Malvern, PA 19355
Mark Thompson
Affiliation:
Silicon Power Corporation, 175 Great Valley Parkway, Malvern, PA 19355
Todd Hansen
Affiliation:
Silicon Power Corporation, 175 Great Valley Parkway, Malvern, PA 19355
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Abstract

High Power asymmetric SiC GTOs (Gate Turn-Off Thyristors) were fabricated on n-type 4H-SiC substrates with multiple epi-layers and were tested to investigate breakdown voltage, maximum current density, switching characteristics, and temperature dependences.

Comparison of breakdown voltages achieved by GTOs with Guard Ring edge termination and GTOs with a proprietary Junction Termination Extension (JTE) fabricated on the same wafer are made. Individual GTOs with a nominal area of 4 mm2 (2 mm × 2 mm) utilizing the JTE were tested in forward bias and found to support over 6 kV at leakage currents of less than 5 μA. In addition, GTOs with a nominal area of 0.25 mm2 (0.5 mm × 0.5 mm) utilizing the JTE were found to support over 7 kV. These blocking voltages are the highest reported for GTOs in SiC. [1–5] Wafer maps of the breakdown voltages for older and newer wafers suggest an improvement of the material. The defect density for the newer wafer is estimated to be greater than the micropipe density.

The on-state characteristics are equally impressive, with 4 mm2 GTOs carrying > 1000 A/cm2. The GTO has a forward voltage drop of 3.66 V at a current density of 300 A/cm2 at room temperature and a forward voltage drop of 3.1 V at 300 A/cm2 at 224 °C. This indicates that on-state losses should not be excessive, even at high current densities and high temperatures.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 742: Symposium K – Silicon Carbide-Materials, Processing, and Devices , 2002 , K7.7
Copyright
Copyright © Materials Research Society 2003

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References

REFERENCES

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