Hostname: page-component-76fb5796d-5g6vh Total loading time: 0 Render date: 2024-04-25T13:11:45.153Z Has data issue: false hasContentIssue false
  • English
  • Français

Vertical Integration: A Confederacy of Alignment, Bonding, and Materials Technologies

Published online by Cambridge University Press:  26 February 2011

Shari Farrens
Shari Farrens*
Affiliation:
Sharon.Farrens@suss.com, SUSS MicroTec, Wafer Bonder Division, 228 Suss Drive, Waterbury Center, VT, 05677, United States, 802 -244-5181, 802 244 1348
Get access

Abstract

Vertical or 3D integration is taking hold in both the CMOS IC industry and the MEMS industry. The need for smaller devices, lower power, increased functionality, and lower cost are driving the market toward chip and wafer level stacking. Equipment suppliers have been faced with numerous challenges to meet the demands of these emerging bonding applications. This paper will discuss the confederacy of alignment, bonding and materials unions that can lead to successful outcomes in integrated manufacturing.

1. Alignment strategies for 3D integration: IR, BSA, and ISA as they pertain to specific bond methods

2. Pros and Cons of 3D Bonding Techniques (Direct bonds, metal, adhesive, and eutectic)

3. Error analysis in alignment of 3D structures

Keywords

bondingsemiconductingmetal
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y04-05
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Moskowitz, N., “3D Wafer Level Interconnect: The Next Wave of Electronic Packaging”, RTI Conference: 3D Architectures for Semiconductor Integration and Packaging, Mecray, Matthew, Bair, Wilfried, and Swinnen, Bart, eds., San Francisco Airport Marriott, Burlingame, CA, Oct. 31-Nov 2, 2006.Google Scholar
2. Kwon, Y., Lu, J-Q., Gutmann, R.J., Kraft, P.P., McDonald, J.F. and Cale, T.S., “Wafer bonding Using Low-K Dielectrics as Bonding Glue in Three-Dimensional Integration, The Electrochemical Society, 2001 Joint Meeting, September 2–7, 2001, San Francisco.Google Scholar
3. Farrens, S. and Hermanowski, J., “Lights-out MEMS Manufacturing”, Adv. Pkg., Aug/Sept 2006, p16–18.Google Scholar