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Ferroelectric 1-T memory device—will it be viable for nonvolatile memory applications?

Published online by Cambridge University Press:  01 February 2011

Jin-Ping Han*
Affiliation:
National Institute of Standards and Technology (NIST), Semiconductor Electronics Division, Gaithersburg, MD 20899, USA
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Abstract

The quest for a nonvolatile memory FET based on the metal-ferroelectric-(insulator)-semiconductor (MF(I)S) gate stack concept has greatly intensified in recent years. In principle, such a memory device (MF(I)S) could be a building block of an ideal memory technology which offers random access, high speed, low power, high density and non-volatility. In practice, however, none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days so far. These results are a far cry from the 10-year retention time requirement for non-volatile memory devices. This paper reveals progress and optimization that grain size, interfacial properties, and crystallinity of the annealed ferroelectric SrBi2Ta2O9 (SBT) films have a strong impact on the size of the memory window, as does the choice of the buffer layer material. The properties of SiN buffer layer sandwiched between SBT and Si are discussed. Switches in the polarization of the ferroelectric SBT play a key role for both the ferroelectric-polarization-dominated and the trapping-dominated memory windows. Preliminary results on MFIS capacitors and transistors are reviewed, limited retention time has been observed. A closer look at the physics of device operation reveals two major causes of the short retention time: (1) depolarization fields; (2) finite gate leakage current and the associated charge trapping. Here, the origins of these problems are analyzed and practical difficulties in attempting to realize nonvolatile ferroelectric 1-T memory devices are illustrated. Two possible solutions have been proposed to circumvent problems associated with the finite retention time in ferroelectric FETtype memories: (1) memory refreshes as done in the FEDRAM cell, (2) single-crystallize the ferroelectric film.

Type
Research Article
Copyright
Copyright © Materials Research Society 2005

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References

[1] Masuoka, F., Assano, M. et al. “A new Flash EEPROM cell using triple polysilicon technology”, IEEE IEDM Tech. Dig., pp.464467 (1984)Google Scholar
[2] Auciello, O., Scott, J. F. and Ramesh, R.The physics of ferroelectric memories”, Physics Today, pp.2227, July 1998.Google Scholar
[3] Derbenwick, G. F. and Isaacson, A. F.Ferroelectric memory: on the brink of breaking through”, IEEE Circuits & Devices, pp.2030, January, 2001.Google Scholar
[4] Yang, B., Lee, S.S. et. al. “Integrated process and reliability for SBT based ferroelectric memoriesJournal of semiconductor technology and Science, Vol.1, No.3, Sept. 2001 Google Scholar
[5] Inomata, K.Present and future of magnetic RAM technologyIEICE TRANSACTIONS ON ELECTRONICS E84C (6), pp.740746 June 2001 Google Scholar
[6] Lai, S. and Lowrey, T.OUM – A 180 nm nonvolatile memory cell element technology for stand alone and embedded applicationIEEE-IEDM 01803 (2001)Google Scholar
[7] Ishiwara, H.Recent progress in FET-type ferroelectric memoriesIEEE-IEDM 03263 (2003)Google Scholar
[8] Broadbridge, C. C., Han, J.-P, et.al. “Microstructure and physical properties of ferroelectric-gate memory capacitors with various buffer layers2001 Spring MRS proceeding (2001)Google Scholar
[9] Broadbridge, C. C., Han, J.-P, et. al. “Impact of processing conditions on the microstructural and Physical Characteristics of Ferroelectric-gate Memory Capacitors”, 2001 MRS Fall Meeting, Boston, MA, Nov. 2001 Google Scholar
[10] Han, J.-P., Guo, X., et al, “Buffer layer dependence of memory effects for SrBi2Ta2O9 on SiIntegrated Ferroelectrics, Vol.34(1–4), pp.15051512 (2000)Google Scholar
[11] Han, J.-P. and Ma, T.P., “SrBi2Ta2O9 memory capacitor on Si with nitride buffer”, Appl. Phys. Lett., Vol.72(10), pp.11851186 (1998)Google Scholar
[12] Han, J.-P., Koo, S. M., Richter, C. A. & Vogel, E. M.Influence of buffer layer thickness on memory effects of SrBi2Ta2O9/SiN/Si structuresAppl. Phys. Lett. Vol.85 (8), pp.14391441 (2004)Google Scholar
[13] Kim, K-H., Han, J.-P., Jung, S.-W. and Ma, T. P., “Ferroelectric DRAM (FEDRAM) FET with metal/ SrBi2Ta2O9/SiN/Si gate structure”, Electron Device Letters, Vol.23, No.2, pp.8284, Feb. 2002 Google Scholar
[14] Wang, X.W., Ma, T.P. et. al. “Highly reliable silicon-nitride thin-films made by jet vapor-depositionJpn. J. Appl. Phys. Part 1 34 (2b), pp.955958 Feb. 1995 Google Scholar
[15] Fleetwood, D.M., “Border traps in MOS deviceIEEE Trans. Nucl. Sci. 39(2), Part 2, pp.269271 (1992)Google Scholar
[16] Tokumitsu, E., Nakamura, R., and Ishiwara, H., “Nonvolatile memory operations of metal-ferroelecrtic-insulator-semiconductor (MFIS) FET's using PLZT/STO/Si (100) structures,” IEEE Electron Device Letters, Vol.18, No.4, pp.160162 (1997)Google Scholar
[17] Yamaguchi, T., Koyama, M., Takashima, A., and Takagi, S., “Improvement of memory characteristics of metal-ferroelectrics/insulating Buffer Layer/semiconductor structures by combination of pulsed laser deposited SrBi2Ta2O9 films and ultra-thin SiN buffer layers,” Jpn. J. Appl. Phys., Vol.39, No.4B, pp.20582062 (2000)Google Scholar
[18] Ma, T. P. and Han, J.-P.“Why is nonvolatile ferroelectric memory field-effect transistor still elusive?Electron Device Letters, Vol.23, No.7 pp.386388, July, (2002)Google Scholar
[19] Black paper C.T. Black et. al. “Suppression of ferroelectric polarization by an adjustable depolarization fieldAppl. Phys. Lett., Vol.71, pp.2041 (1997)Google Scholar
[20] Takahashi, M. et. al. “Analysis and improvement of retention time of memorized state of metal-ferroelectric-insulator-semiconductor structure for ferroelectric gate FET memoryJpn. J. Appl. Phys. Vol.40, pp.29232927, Part1, No.4B, April, 2001 Google Scholar
[21] SIA, The national technology roadmap for semiconductors technology needs: Semiconductor Industry Associations (SIA), 2001.Google Scholar
[22] Lin, A., Hong, X., Wood, V., Verevkin, A. A., Ahn, C.H., McKee, R.A., Walker, F.J., and Specht, E.D., “Epitaxial growth of Pb(Zr0.2Ti0.8)O3 on Si and its nanoscale piezoelectric properties”, Appl. Phys. Lett., Vol.78, pp.2034 (2001)Google Scholar
[23] Gong, W., li, J. F., Chu, X.C., Gui, Z.L., and Li, L.T.Single-crystal Nb-doped Pb(Zr, Ti)O3 thin films on Nb-doped SrTiO3 wafers with different orientationsAppl. Phys. Lett., Vol.85 (17), pp.38183820 (2001)Google Scholar
[24] Ma, T.P. and Han, J-P, “A Ferroelectric Dynamic Random Access Memory” U.S. Patent 6067244 (2000)Google Scholar
[25] Han, J-P. and Ma, T.P.A capactor-less ferroelectric DRAM cell (FEDRAM)Integrated Ferroelectrics, Vol.27, No.1–4, pp.10531062 (1999)Google Scholar