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Study of CoSix Spike Leakage for 0.1-um CMOS

Published online by Cambridge University Press:  14 March 2011

Ken-ichi Goto
Ken-ichi Goto*
Affiliation:
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
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Abstract

We have clarified a new leakage mechanism in Co salicide process for the ultra-shallow junctions of 0.1-um CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents generate from many localized points that are randomly distributed in the junction area, and not from the junction edge. We successfully verified our localized leakage model using Monte Carlo simulation. We identified abnormal CoSix spiking growth under the Co silicide film, as being the origin of the localized leakage current. These CoSix spikes grow rapidly only during annealing between 400°C and 450°C when Co2Si phase is formed. These spikes never grow during annealing at over 500°C, and decrease with high temperature annealing over 500°C. A minimum leakage current can be achieved by optimized annealing at between 800°C and 850°C for 30 sec. This is because a trade-off between reducing the CoSix spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900°C.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 611: Symposium C – Gate Stack & Silicide Issues in Silicon Processing , 2000 , C9.1.1
Copyright
Copyright © Materials Research Society 2000

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References

REFERENCES

[1] Yamazaki, T., Goto, K., Fukano, T., Nara, Y., Sugii, T., and Ito, T., “21 ps switching 0.1-um-CMOS at room temperature using high performance Co salicide process”, in IEDM Tech. Dig., 1993, pp.906–909.Google Scholar
[2] Goto, K., Yamazaki, T., Fushida, A., Inagaki, S., and Yagi, H., “Optimization of salicide process for 0.1-um CMOS devices”, in Symp. VLSI Tech., 1994, pp. 119–120.Google Scholar
[3] Lasky, J. B., Nakos, J. S., Cain, O. J., and Geiss, P. J., “Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2; IEEE Trans. Electron Devices, vol. 38, pp. 262–271, Feb. 1991.Google Scholar
[4] Berti, A. C. and Bolkhovsky, V., “A manufacturable process for the formation of self aligned cobalt silicide in submicronmeter CMOS technology”, VMIC Conf. Dig., 1992, pp. 267–273.Google Scholar
[5] Goto, K., Fushida, A., Watanabe, J., Sukegawa, T., Kawamura, K., Yamazaki, T., and Sugii, T., “Leakage mechanism and optimized conditions of Co salicide process for deep submicron CMOS devices”, in IEDM Tech. Dig., 1995, pp. 906–909.Google Scholar