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Defect Reduction in GaAs Epilayers on Si Substrates Using Strained Layer Superlattices

Published online by Cambridge University Press:  28 February 2011

N. El-Masry ,
N. Hamaguchi ,
J.C.L. Tarn ,
N. Karam ,
T.P. Humphreys ,
D. Moore ,
S.M. Bedair ,
J. W. Lee  and
J. Salerno
N. El-Masry
Affiliation:
Electrical and Computer Engineering DepartmentNorth Carolina State UniversityRaleigh, North Carolina 27695
N. Hamaguchi
Affiliation:
Electrical and Computer Engineering DepartmentNorth Carolina State UniversityRaleigh, North Carolina 27695
J.C.L. Tarn
Affiliation:
Electrical and Computer Engineering DepartmentNorth Carolina State UniversityRaleigh, North Carolina 27695
T.P. Humphreys
Affiliation:
Electrical and Computer Engineering DepartmentNorth Carolina State UniversityRaleigh, North Carolina 27695
D. Moore
Affiliation:
Electrical and Computer Engineering DepartmentNorth Carolina State UniversityRaleigh, North Carolina 27695
S.M. Bedair
Affiliation:
Electrical and Computer Engineering DepartmentNorth Carolina State UniversityRaleigh, North Carolina 27695
J. W. Lee
Affiliation:
Kopin Corporation Taunton, Massachusetts
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Abstract

InxGa11-xAs-GaAsl-yPy strained layer superlattice buffer layers have been used to reduce threading dislocations in GaAs grown on Si substrates. However, for an initially high density of dislocations, the strained layer superlattice is not an effective filtering system. Consequently, the emergence of dislocations from the SLS propagate upwards into the GaAs epilayer. However, by employing thermal annealing or rapid thermal annealing, the number of dislocation impinging on the SLS can be significantly reduced. Indeed, this treatment greatly enhances the efficiency and usefulness of the SLS in reducing the number of threading dislocations.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 91: Symposium A – Heteroepitaxy on Silicon II , 1987 , 99
Copyright
Copyright © Materials Research Society 1987

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