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Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

Published online by Cambridge University Press:  15 March 2011

J.-Q. Lu ,
G. Rajagopalan ,
M. Gupta ,
T.S. Cale  and
R.J. Gutmann
J.-Q. Lu
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Hyperintegration Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York-12180, USA, luj@rpi.edu
G. Rajagopalan
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Hyperintegration Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York-12180, USA
M. Gupta
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Hyperintegration Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York-12180, USA
T.S. Cale
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Hyperintegration Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York-12180, USA
R.J. Gutmann
Affiliation:
Focus Center-New York, Rensselaer: Interconnections for Hyperintegration Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York-12180, USA
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Abstract

Monolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 816: Symposium K – Advances in Chemical-Mechanical Polishing , 2004 , K7.7
Copyright
Copyright © Materials Research Society 2004

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