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Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

Published online by Cambridge University Press:  10 February 2011

Siguang Ma
Affiliation:
CICFAR, Department of Electrical Engineering, National University of Singapore, Singapore 119260.
Yaohui Zhang
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore 117864
M. F. Li
Affiliation:
CICFAR, Department of Electrical Engineering, National University of Singapore, Singapore 119260.
Weidan Li
Affiliation:
LSI Logic Co, Santa Clara, CA 95054, USA
J. L. F. Wang
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore 117864
Andrew C. Yen
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore 117864
George T. T. Sheng
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore 117864
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Abstract

In this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

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