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The Influence of Interface Traps on the High Frequency and High Temperature Performance of SiC Field Effect Transistors

Published online by Cambridge University Press:  10 February 2011

H. Aydin ,
M. W. Dryfuse  and
M. Tabib-Azar
H. Aydin
Affiliation:
Electrical Eng. & Applied Physics Dept. Case Western Reserve University Cleveland, Ohio 44106
M. W. Dryfuse
Affiliation:
Electrical Eng. & Applied Physics Dept. Case Western Reserve University Cleveland, Ohio 44106
M. Tabib-Azar
Affiliation:
Electrical Eng. & Applied Physics Dept. Case Western Reserve University Cleveland, Ohio 44106
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Abstract

Fast and slow interface traps can considerably deteriorate the performance of field effect transistors. Slow interface traps, by slowly changing their charge occupancy, contribute to a drift in the quiescent operation point of the transistor, while fast traps deteriorate the device performance by contributing to both amplitude and phase current noise. They also result in a non-equilibrium surface depletion layer between gate and source which increases the gate-to-source parasitic resistance and deteriorates the device transconductance. We examine these different effects and present some preliminary data regarding interface traps in boron-doped 611-SiC.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 410: Symposium S – Covalent Ceramics III-Science and Technology of Non-Oxides , 1995 , 73
Copyright
Copyright © Materials Research Society 1996

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References

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