Hostname: page-component-76fb5796d-vfjqv Total loading time: 0 Render date: 2024-04-25T11:31:34.293Z Has data issue: false hasContentIssue false

Electronic Characterization of Dislocations in Rtcvd Germanium-Silicon/Silicon Grown by Graded Layer Epitaxy

Published online by Cambridge University Press:  22 February 2011

P.N. Grillot
Affiliation:
Dept. of Electrical Engineering, The Ohio State University, Columbus, OH 43210
S.A. Ringel
Affiliation:
Dept. of Electrical Engineering, The Ohio State University, Columbus, OH 43210
G.P. Watsona
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ 07974
E.A. Fitzgerald
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ 07974
Y.H. Xie
Affiliation:
AT&T Bell Laboratories, Murray Hill, NJ 07974
Get access

Abstract

Carrier trapping and recombination activity have been studied with DLTS and EBIC in RTCVD grown compositionally graded Ge0.3Si0.7/Si heterostructures. DLTS peak height is found to vary with applied bias, and the bias conditions used indicate that at least one peak is present in the homoepitaxial Si buffer layer and perhaps the substrate as well. Variations in EBIC contrast as a function of reverse bias, and DLTS fill pulse experiments both indicate that the DLTS peaks observed are dislocation related. Moreover, the bias dependent decrease in DLTS peak height is observed to occur at different rates for different peaks, indicating a possible connection between certain DLTS peaks and dislocation orientation or type. Activation energies of one electron trapping center and one hole trapping center add up to roughly the expected bandgap in a relaxed GexSi1−x, alloy with x ≦ 0.3, indicating that the electron and hole trapping centers observed with DLTS may, in fact, be associated with the R-G center observed by EBIC.

Type
Research Article
Copyright
Copyright © Materials Research Society 1994

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Watson, G.P., Fitzgerald, E.A., Xie, Y., and Monroe, D.P., submitted to J. Appl. Phys.Google Scholar
2. Watson, G.P., Ast, D.G., Anderson, T.J., Pathangey, B., and Hayakawa, Y., J. Appl. Phys., 71, 3399 (1992).Google Scholar
3. Wosinski, T., J. Appl. Phys., 65, 1566 (1989).Google Scholar
4. Omling, P., Weber, E.R., Montelius, L., Alexander, H., and Michel, J., Phys. Rev. B, 32, 6571 (1985).Google Scholar
5. Kimerling, L.C. and Patel, J.R., in VLSI Electronics, vol. 12, edited by Einspruch, N.G., (Academic Press, Orlando, 1985) p. 223.Google Scholar
6. Kveder, V.V., Osipyan, Y.A., Schroter, W., and Zoth, G., Phys. Stat. Sol. A, 72, 701 (1982).Google Scholar
7. Figielski, T., Solid State Electron., 21, 1403 (1978).Google Scholar
8. Grillot, P.N., Ringel, S.A., Watson, G.P., and Fitzgerald, E.A., manuscript in preparation.Google Scholar