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Taguchi Design of Experiment Enabling the Reduction of Spikes on the Sides of Patterned Thin Films for Tunnel Junction Fabrication

Published online by Cambridge University Press:  22 June 2017

Pawan Tyagi ,
Edward Friebe ,
Beachrhell Jacques ,
Tobias Goulet ,
Stanley Travers  and
Francisco J Garcia-Moreno
Pawan Tyagi*
Affiliation:
University of the District of Columbia, Department of Mechanical Engineering, 4200 Connecticut Avenue NW Washington DC-20008, USA
Edward Friebe
Affiliation:
University of the District of Columbia, Department of Mechanical Engineering, 4200 Connecticut Avenue NW Washington DC-20008, USA
Beachrhell Jacques
Affiliation:
University of the District of Columbia, Department of Mechanical Engineering, 4200 Connecticut Avenue NW Washington DC-20008, USA
Tobias Goulet
Affiliation:
University of the District of Columbia, Department of Mechanical Engineering, 4200 Connecticut Avenue NW Washington DC-20008, USA
Stanley Travers
Affiliation:
University of the District of Columbia, Department of Mechanical Engineering, 4200 Connecticut Avenue NW Washington DC-20008, USA
Francisco J Garcia-Moreno
Affiliation:
Department of Energy’s National Security Campus, managed by Honeywell, 14520 Botts Road Kansas City, MO 64147
*
*(Email: ptyagi@udc.edu)
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Abstract

Photolithographically patterned thin films often possess unwanted spikes along the side edges. These spikes are a significant issue for the development of spinvalve memory, tunnel junction based molecular devices, and micro-electromechanical systems. Here, we report a very simple, economical, and fast way of creating an optimum photoresist profile for the production of spike-free patterned films. This approach is based on performing a soaking step in the positive-photoresist’s developer solution before the UV exposure. However, the success of this method depends on multiple photolithography factors: photoresist thickness (governed by spin speed), soft baking temperature, soaking time in developer, and exposure time. In this paper, we report our systematic experiments to study the effect of these factors by following the L9 experimental scheme of the Taguchi Design of experiment (TDOE) approach. The L9 experiment scheme effectively accommodated the study of four photolithography factors, each with three levels. After performing photolithography as per L9 TDOE scheme, we sputter deposited 20 nm Tantalum to check the side edge profile of the patterned film by atomic force microscope (AFM). We measured the heights of the spikes along the thin film edges. We utilized spike height as the desired property and chose “smaller the better” criteria for the TDOE analysis. TDOE enabled us to understand the relative importance of the parameters, relationship among the parameters, and impact of the various levels of the parameters on the thin film edge profile. TDOE analysis yielded an optimum combination of levels for the four photolithography factors. The optimum combination of photolithography factors included spin speed 4000 rpm, 100 °C soft baking temperature, 60 sec pre-soaking in the developer solution, and 15 sec UV exposure. We validated the TDOE by AFM and observed spike free patterned films. We also made complete tunnel junction devices by utilizing the optimized photolithography factors for the bottom electrode and obtained excellent tunneling behavior. In summary, this study provides a very simple, economical, and fast photolithography approach for creating optimum photoresist profile for the micro-nano scale devices and electromechanical structures.

Keywords

barrier layerelectrical propertiesphysical vapor deposition (PVD)
Type
Articles
Information
MRS Advances , Volume 2 , Issue 52: Electronic Devices and Materials , 2017 , pp. 3025 - 3030
Copyright
Copyright © Materials Research Society 2017 

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References

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