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Patterned wafers backside thinning for 3-D Integration and multilayer stack achievement by direct wafer bonding

Published online by Cambridge University Press:  01 February 2011

Barbara Charlet ,
Antoine Chiteboun ,
Marc Zussy ,
Laurent Bally ,
Patrick Leduc  and
Myriam Assous
Barbara Charlet
Affiliation:
Barbara.Charlet@cea.fr, CEA - DRT/LETI, MINATEC, 17, rue des Martyrs, Grenoble, F 38054, France, +33438784757, +33438785169
Antoine Chiteboun
Affiliation:
antoine.chiteboun@yahoo.fr, CEA - DRT/LETI, MINATEC, 17, rue des Martyrs, Grenoble, F 38054, France
Marc Zussy
Affiliation:
marc.zussy@cea.fr, CEA - DRT/LETI, MINATEC, 17, rue des Martyrs, Grenoble, F 38054, France
Laurent Bally
Affiliation:
laurent.bally@cea.fr, CEA - DRT/LETI, MINATEC, 17, rue des Martyrs, Grenoble, F 38054, France
Patrick Leduc
Affiliation:
patrick.leduc@cea.fr, CEA - DRT/LETI, MINATEC, 17, rue des Martyrs, Grenoble, F 38054, France
Myriam Assous
Affiliation:
myriam.assous@cea.fr, CEA - DRT/LETI, MINATEC, 17, rue des Martyrs, Grenoble, F 38054, France
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Abstract

Scaling down the devices to keep increasing the integrated circuits (ICs) performance at the rate defined by Moore's [1] law becomes more and more difficult and so costly that new circuits architectures and new integration technologies are investigated. One of the most promising ways in integration technology is the vertical stacking of circuits, also called “3D Integration”. One of the challenges in this technology is the patterned substrate backside thinning. Compatibility with the whole 3D Integration process has to be guaranteed, the existing circuit has to be kept intact and the bonding interface mustn't be damaged. In this study we discuss some experimental results of wafer thinning by grinding and polishing of molecular bonded silicon wafers applied to 3D Integration [2-4]. The wafer with patterned copper interconnections are stacked by direct SiO2 bonding and thinned down on one backside. These stacks are then bonded again to one or two circuits via a deposited oxide on the thinned surface. The top bulk Si surface was thinned down again on one backside, giving a multi layers stack. This wafer level vertical assembly demonstrates the possibility to adjust the remaining Silicon thickness to small values (<15μm) and then bond the thinned surface to achieve multiple layer 3D structure.

Keywords

microelectronicsthin filmmicrostructure
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1079: Symposium N – Materials and Processes for Advanced Interconnects for Microelectronics , 2008 , 1079-N06-10
Copyright
Copyright © Materials Research Society 2008

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References

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