Hostname: page-component-8448b6f56d-xtgtn Total loading time: 0 Render date: 2024-04-23T22:44:32.350Z Has data issue: false hasContentIssue false
  • English
  • Français

Reactive Ion Etching of WSi0.6 Gates for GaAs MESFETS

Published online by Cambridge University Press:  28 February 2011

C. L. Lin  and
Peter D. Hoh
C. L. Lin
Affiliation:
IBM Thomas J.Watson Research Center, P.O.Box 218, Yorktown Heights, New York, 10598
Peter D. Hoh
Affiliation:
IBM Thomas J.Watson Research Center, P.O.Box 218, Yorktown Heights, New York, 10598
Get access

Abstract

A process for reactive ion etching of 1μm and sub-micron WSi0.6 gates for GaAs MESFET integrated circuits has been developed.Using a CF4/O2 plasma, a 200am film of WSi0.6 could be etched in ≃ 5 minutes.This is sufficiently long for accurate process monitoring.A vertical edge profile has been obtained which is desirable for a self-aligned MESFET process.To achieve the vertical edge, careful control of the degree of over etch was necessary.This was accomplished by monitoring the intensity profile of a laser beam reflected from the wafer being etched.The widths of lines etched in WSi0.6 closely matched those of the resist pattern.Both 1μm and sub-micron FET's were fabricated.with excellent linewidth control and electrical characteristics

Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 68: Symposium C – Plasma Processing , 1986 , 47
Copyright
Copyright © Materials Research Society 1986

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Doerbeck, F.H., “A planar gallium arsenide FET with a self-aligned Schottky barrier gate,” presented at the 3rd Int.Symp.on GaAs and Related Compounds, Aachen, Germany, OcL 1970.Google Scholar
2. Yokoyama, N., Mimura, T., Fukuta, M., and Ishikawa, H., “A self-aligned source/drain planar device for ultrahigh-speed GaAs MESFET VLSI's,” in 1981 Int.Solid-State Circuits Conf., Dig.Tech.Papers, Feb.1981, pp.218–9.Google Scholar
3. Abe, M., Mimura, T., Yokoyama, N., and Ishikawa, H., “New technology towards GaAs LSI/VLSI for computer applications,” IEEE Trans.Electron Devices, vol.ED–29, pp.1088–93, 1982.CrossRefGoogle Scholar
4. Willianms, R., Gallium Arsenide Processing Techniques, Artech House, 1984.Google Scholar
5. Yokoyama, N., Ohnishi, T., Onodera, H., Shinoki, T., Shibatomi, A., Ishikawa, H. “A GaAs IK Ram using Tungsten-Silicide Gate Self-Alignment Technology” IEEE Internat.onal Solid-State Circuits Conference pp.44–45, 1983 CrossRefGoogle Scholar
6. Coburn, J.W., Plasma Etching and Reactive Ion Etching, American Vacuum Society, American Institute of Physics, Inc., 1982.Google Scholar
7. Harshbarger, W.R. et al, Appl.Spectrosc. 31 201 (1977)CrossRefGoogle Scholar
8. Mogab, C.I., Adams, A.C., Flamm, D.L., J. Appl. Phys. 49 3796 (1978)Google Scholar