Hostname: page-component-8448b6f56d-42gr6 Total loading time: 0 Render date: 2024-04-19T22:35:22.182Z Has data issue: false hasContentIssue false
  • English
  • Français

Prevention of Corner Voiding in Selective CVD Deposition of Titanium Silicide on SOI Device

Published online by Cambridge University Press:  10 February 2011

Jer-shen Maa ,
Bruce Ulrich ,
Lisa Stecker ,
Greg Stecker  and
Sheng Teng Hsu
Jer-shen Maa
Affiliation:
Sharp Laboratories of America, Camas, WA 98607
Bruce Ulrich
Affiliation:
Sharp Laboratories of America, Camas, WA 98607
Lisa Stecker
Affiliation:
Sharp Laboratories of America, Camas, WA 98607
Greg Stecker
Affiliation:
Sharp Laboratories of America, Camas, WA 98607
Sheng Teng Hsu
Affiliation:
Sharp Laboratories of America, Camas, WA 98607
Get access

Abstract

In the application of selective CVD of titanium silicide to SOI devices, voids were observed at the bottom corner of the spacers, which caused reduction of drain current and in extreme cases formed an open circuit. Test structures were constructed to monitor void formation. It was found the voiding became serious when the thickness of the Si film was reduced. Adjusting the deposition condition by reducing the TiCi4 flow rate or by using a two-step deposition process was able to significantly reduce the chance of void formation. On very thin Si films, voiding can be prevented by depositing a selective Si layer prior to silicide deposition.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 564: Symposium N – Advanced Interconnects and Contacts , 1999 , 29
Copyright
Copyright © Materials Research Society 1999

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Maa, J.-S., Proc. 11 th VLSI Multilevel Interconnection Conference, Santa Clara, 1994, p. 484.Google Scholar
2. Chen, J., Colinge, J.-P., Flandre, D., Gillon, R., Raskin, J.P. and Vanhoenacker, D., J. Electrochem. Soc., 144, 1997, 2437.10.1149/1.1837833Google Scholar
3. Azuma, K., Kishi, A., Tanigawa, M., Kaneko, S., Naka, T., Ishihama, A., Iguchi, K. and Sakiyama, K., Proc. 1995 International SOI Conference, p30.Google Scholar
4. Ilderem, V. and Reif, R., J. Electrochem. Soc., 135, 1988, 2437.10.1149/1.2095387Google Scholar
5. Regolini, J.L., Bensahel, D., Bomchil, G. and Mercier, J., Appl. Surf Sci., 38, 1989, 408.10.1016/0169-4332(89)90561-8Google Scholar
6. Bouteville, A., Royer, A. and Remy, J.C., J. Electrochem. Soc., 134, 1987, 2437.10.1149/1.2100825Google Scholar
7. Bouteville, A., Attuyt, C. and Remy, J.C., Appl. Surf. Sci., 53, 1991, 11.10.1016/0169-4332(91)90235-CGoogle Scholar
8. Gladden, D.B., Weintraub, C.E. and Öztürk, M.C., Mat. Res. Soc. Sym. Proc., Vol. 402, 1996, p295.10.1557/PROC-402-295Google Scholar
9. Fang, H., Öztürk, M. C. and Seebauer, E.G., Mat. Res. Soc. Sym. Proc., Vol. 514,1998, p231.10.1557/PROC-514-231Google Scholar
10. Saito, K., Amazawa, T. and Arita, Y., J. Electrochem. Soc., 140, 1993, 2437.Google Scholar
11. Engqvist, J., Jansson, U., Lu, J. and Carlsson, J.-O., J. Vac. Sci. Technol., A12, 1994, 161.10.1116/1.578914Google Scholar
12. Maa, J.-S., Ulrich, B., Hsu, S.T. and Stecker, G., Thin Solid Films, 332, 1998, 412.10.1016/S0040-6090(98)01015-3Google Scholar
13. Colinge, J.-P., Silicon-On-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Boston, 1997, p123.10.1007/978-1-4757-2611-4_5Google Scholar