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A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching

Published online by Cambridge University Press:  01 February 2011

M. Q. Huda  and
K. Sakamoto
M. Q. Huda
Affiliation:
Nanoelectronics Research Institute National Institute of Advanced Industrial Science and Technology Central 2, 1-1-1 Umezono, Tsukuba 305-8568, Japan Email:mq-huda@aist.go.jp
K. Sakamoto
Affiliation:
Nanoelectronics Research Institute National Institute of Advanced Industrial Science and Technology Central 2, 1-1-1 Umezono, Tsukuba 305-8568, Japan Email:mq-huda@aist.go.jp
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Abstract

A process involving implantation mediated selective etching has been developed for Source/Drain elevation of CMOS devices. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO2 structure by chemical vapor deposition (CVD) at 700°C. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical <100> channeling direction. A short duration post-anneal at 420°C was usedfor structural recovery of the silicon layer. Polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 765: Symposium D – CMOS Front-End Materials and Process Technology , 2003 , D1.7
Copyright
Copyright © Materials Research Society 2003

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