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High quality and high speed cutting of 4H-SiC JFET wafers including PCM structures by using Thermal Laser Separation

Published online by Cambridge University Press:  10 June 2014

Dirk Lewke
Affiliation:
Fraunhofer Institute for Integrated Systems and Device Technology IISB; Erlangen, Germany.
Matthias Koitzsch
Affiliation:
Fraunhofer Institute for Integrated Systems and Device Technology IISB; Erlangen, Germany.
Karl Otto Dohnke
Affiliation:
Infineon Technologies AG; Erlangen, Germany
Martin Schellenberger
Affiliation:
Fraunhofer Institute for Integrated Systems and Device Technology IISB; Erlangen, Germany.
Hans-Ulrich Zuehlke
Affiliation:
3D-Micromac AG; Chemnitz, Germany
Roland Rupp
Affiliation:
Infineon Technologies AG; Erlangen, Germany
Lothar Pfitzner
Affiliation:
Fraunhofer Institute for Integrated Systems and Device Technology IISB; Erlangen, Germany.
Heiner Ryssel
Affiliation:
Fraunhofer Institute for Integrated Systems and Device Technology IISB; Erlangen, Germany.
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Abstract

The silicon carbide (SiC) market is gaining momentum hence productivity in device manufacturing has to be improved. The current transition from 100 mm SiC-wafers to 150 mm SiC-wafers requires novel processes in the front-end as well as the back-end of SiC-chip production. Dicing of fully processed SiC-wafers is becoming a bottleneck process since current state-of-the-art mechanical blade dicing faces heavy tool wear and achieves low throughput due to low feed rates in the range of only a few mm/s. This paper presents latest results of the novel dicing technology Thermal Laser Separation (TLS) applied for separating SiC-JFETs. We demonstrate for the first time that TLS is capable of dicing fully processed 4H-SiC wafers, including back side metal layer stacks, process control monitoring (PCM), and metal structures inside the dicing streets with feed rates up to 200 mm/s. TLS thus paves the way to efficient dicing of 150 mm SiC-wafers.

Type
Articles
Copyright
Copyright © Materials Research Society 2014 

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References

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