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Physically Based Compact Model for Segmented a-Si:H n-i-p Photodiodes

Published online by Cambridge University Press:  01 February 2011

Jeff Hsin Chang
Affiliation:
jhchang@gmail.com, Carestream Health, Research and Innovation, 1049 Ridge Road West, Rochester, NY, 14615, United States, (585) 413-3684
Timothy Tredwell
Affiliation:
timothy.tredwell@carestreamhealth.com, Carestream Health Inc., 1049 Ridge Road West, Rochester, NY, 14615, United States
Gregory Heiler
Affiliation:
gregory.heiler@carestreamhealth.com, Carestream Health Inc., 1049 Ridge Road West, Rochester, NY, 14615, United States
Yuri Vygranenko
Affiliation:
yuriy@venus.uwaterloo.ca, University of Waterloo, 200 University Avenue West, Waterloo, M1S 3H3, Canada
Denis Striakhilev
Affiliation:
dstriakhilev@venus.uwaterloo.ca, University of Waterloo, 200 University Avenue West, Waterloo, M1S 3H3, Canada
Kyung Ho Kim
Affiliation:
khkim@venus.uwaterloo.ca, University of Waterloo, 200 University Avenue West, Waterloo, M1S 3H3, Canada
Arokia Nathan
Affiliation:
anathan@ucl.ac.uk, London Centre for Nanotechnology, University College, London, WC1H OAH, United Kingdom
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Abstract

Hydrogenated amorphous silicon (a–Si:H) n–i–p photodiodes are used as pixel sensor elements in large-area flat-panel detectors for medical imaging diagnostics. Accurate model of the sensor plays an imperative role in determining the performances of the detector systems as well as ascertaining design issues prior to production. This work presents the formulation of a compact model for segmented a–Si:H n–i–p photodiodes suitable for circuit-level simulation. The underlining equations of the model are based on device physics where the parameters are extracted from pertinent measurement results of previously fabricated a–Si:H n–i–p photodiodes. Furthermore, the implemented model allows photoresponse simulation with the addition of an external current source. Results of the simulation demonstrated excellent matching with measurement data for different photodiode sizes at various temperatures. The model is implemented in Verilog-A and simulated under Cadence Virtuoso design environment using device geometry and extracted parameters as inputs. The model formulation and parameter extraction process, as well as measurements and simulation results are presented.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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References

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