Due to the wide bandgap and other key materials properties of 4H-SiC, SiC MOSFETsoffer performance advantages over competing Si-based power devices. For example,SiC can more easily be used to fabricate MOSFETs with very high voltage ratings,and with lower switching losses. Silicon carbide power MOSFET development hasprogressed rapidly since the market release of Cree’s 1200V 4H-SiCpower MOSFET in 2011. This is due to continued advancements in SiC substratequality, epitaxial growth capabilities, and device processing. For example,high-quality epitaxial growth of thick, low-doped SiC has enabled thefabrication of SiC MOSFETs capable of blocking extremely high voltages (up to15kV); while dopant control for thin highly-doped epitaxial layers has helpedenable low on-resistance 900V SiC MOSFET production. Device design andprocessing improvements have resulted in lower MOSFET specific on-resistance foreach successive device generation. SiC MOSFETs have been shown to have a longdevice lifetime, based on the results of accelerated lifetime testing, such ashigh-temperature reverse-bias (HTRB) stress and time-dependent dielectricbreakdown (TDDB).

In this report we present results comparing lateral MOSFET properties of devices fabricated on Si-face (0001) and A-face (11-20) 4H-SiC, with nitric oxide passivation anneals. We observe a field-effect mobility of 33 cm2/V.s on p-type 5×1015 doped Si-face. These devices have a peak field-effect mobility which increases with temperature, indicative of a channel mobility limited by coulomb scattering. On 1×1016 p-type A-face SiC, the peak channel mobility is observed to be 80 cm2/V.s, with a negative temperature dependence, indicating that phonon-scattering effects dominate, with a much lower density of shallow acceptor traps. This > 2x higher channel mobility would result in a substantial decrease in on-resistance, hence lower power losses, for 4H-SiC power MOSFETs with voltage ratings below 2 kV. However, MOS C-V and gate leakage measurements indicate very different oxide and interface quality on each SiC face. For example, the Fowler-Nordheim (FN) conduction-band (CB) barrier height for electron tunneling at the SiO2/SiC interface is 2.8 eV on Si-face SiC, while it is 2.5 eV or less on A-face SiC. For the valence-band side, the effective FN barrier height at the valence-band (VB) side of only 1.6 eV on A-face SiC, while the VB barrier height is about 3.1 eV on Si-face SiC. Moreover, C-V of the MOS gate on A-face indicates the presence of a high-density of deep hole traps. It is apparent that oxides on alternative crystal faces, very promising in terms of channel mobility, require further study for complete understanding and control of the interface properties.

Lateral nMOSFETs have been fabricated on 4H-SiC utilizing deposited dielectrics and gate-last processing. A bi-layer dielectric was utilized consisting of thin nitrided SiO2 covered by 25nm of Al2O3 deposited using atomic layer deposition. Field-effect mobility and threshold voltage (VT) were found to vary with SiC nitric oxide (NO) anneal temperature. High peak mobility values of 106 cm2/V·s were obtained, with a corresponding VT of 0.8 V, using an 1175 °C 20 min NO anneal of the SiC before Al2O3 deposition. Constant voltage stressing (CVS) of the gate (3 MV/cm) for 1000s induces a VT increase of only 0.12 V for the devices stressed at RT, whereas a VT shift of 0.34 V occurs for devices stressed at 150 °C. Heating unstressed devices to 200 °C reveals a stable VT with temperature. Negative charge in the gate region allows for the attainment of positive VT, while VT stability does not suffer.

The interface and electrical properties of HfAlO dielectric formed by atomic layer deposition (ALD) on sulfur-passivated GaAs were investigated. X-ray photoelectron spectroscopy (XPS) revealed the absence of arsenic oxides at the HfAlO/GaAs interface after dielectric growth and post-deposition annealing at 500 °C. A minimal increase in the amount of gallium oxides at the interface was detected between the as-deposited and annealed conditions highlighting the effectiveness of HfAlO in suppressing gallium oxide formation. An equivalent oxide thickness (EOT) of ∼ 2 nm has been achieved with a gate leakage current density of less than 10-4 A/cm2. These results testify a good dielectric interface with minimal interfacial oxides and open up potential for further investigation of HfAlO/GaAs gate stack properties to determine its viability for n-channel MOSFETs.

The properties of lanthanum silicate (LaSiOx) gate stacks on GaAs substrates have been examined, comparing different GaAs pretreatments; namely a) as-received, b) HCl-treated, and c) sulphur-treated. X-ray photoelectron spectroscopy of the As 3d, Ga 3d, and Ga 2p binding energy peaks were used to reveal the chemical nature of the stacks. After a 400 °C in situ anneal in 10−6 torr pO2, the LaSiOx chemically reduces the As oxides from the as-received GaAs, while Ga oxide species remain. HCl and S-treated GaAs similarly show no As oxides, and a much smaller degree of Ga oxides than the as-received case. The Ga-S bonding may be responsible for lowering the tendency towards Ga oxidation for the S-treated case. On p-type, Zn-doped GaAs, 3.0 nm lanthanum silicate films produce MOS device EOT values of 2.38 nm, 1.51 nm, and 1.37 nm, on as-received, HCl-treated, and S-treated substrates, respectively. The high EOT for the as-received GaAs corresponds to the thicker Ga oxide and elemental As at the interface. The decreases in both Ga oxide and elemental As at the interface of the S-treated stack appears to be related to it having the lowest EOT devices.

High-dielectric constant (high-κ) oxide growth on hexagonal-GaN (on sapphire) is examined for potential use in enhancement-mode metal oxide semiconductor field effect transistor (MOSFET). Enhancement-mode MOSFET devices (ns > 4×1013 cm−2) offer significant performance advantages, such as greater efficiency and scalability, as compared to heterojunction field effect transistor (HFET) devices for use in high power and high frequency GaN-based devices. High leakage current and current collapse at high drive conditions suggests that the use of a high-κ insulating layer is principle for enhancement-mode MOSFET development. In this work, rare earth oxides (Sc, La, etc.) are explored due to their ideal combination of permittivity and high band gap energy. However, a substantial lattice mismatch (9-21%) between the rare earth oxides and the GaN substrate results in mid-gap defect state densities and growth dislocations. The epitaxial growth of the rare earth oxides by molecular beam epitaxy (MBE) on native oxide passivated-GaN is examined in an effort to minimize these growth related defects and other growth-related limitations. Growth of the oxide on GaN is characterized analytically by RHEED, XRD, and XPS. Preliminary MOS electrical analysis of a 50 Å La2O3 on GaN shows superior leakage performance as compared to significantly thicker Si3N4 dielectric.

The consequence of tungsten metal purity on the electrical properties of an annealed MOS gate stack with a lanthanum silicate gate dielectric has been investigated. Optimization of the electrical and physical properties of a device with any given dielectric requires the proper choice of metal gate electrode and capping layer. This study is intended to show the importance of tungsten processing optimization and subsequent effects on the equivalent oxide thickness, fixed charge, and density of interface states of La-Si-O gate dielectric MIS devices. In the experiment, La-Si-O films of physical thickness of 1.6 nm were deposited on a Si substrate, subsequently depositing TaN as the gate electrode and W as a capping layer. A post metallization anneal in flowing nitrogen at 1000°C for short times resulted in widely different measured properties of the MIS devices, dependent on the quality of the tungsten deposited. XRD and SIMS profiles of the gate stacks showed a clear relationship between concentration of oxygen and processing of the tungsten. A 1000°C, 10 sec anneal resulted in an EOT change from 1.1 nm to 2.2 nm on gate stacks with low and high oxygen concentration in the tungsten, respectively. Defect densities decreased with increased anneal temperature and time, and annealing with low oxygen-concentration tungsten resulted in higher effective fixed charge. SIMS data suggests that oxygen in the tungsten diffuses to the Si/La-Si-O interface through the TaN electrode, resulting in the observed differences in the defect densities and EOT.

MgO thin films were deposited on silicon and sapphire substrates using ion-beam reactive sputtering. Films have been analyzed using x-ray diffraction, transmission electron microscopy, and atomic force microscopy. Highly oriented (100) MgO films have been obtained on Si (100) substrates. The in-plane orientation is predominantly [100]MgO//[100]Si, although a twist of up to ±10° between grains is observed. Epitaxial films of MgO were deposited on four different orientations of sapphire. The MgO film orientation was (111) on c-cut (0001) Al2O3 and exhibited double positioning boundaries in TEM analysis. On r-cut (1102) Al2O3, the MgO appeared to be oriented (730) with tilt and twist of ±2° between the grains. Epitaxial MgO films oriented (110) and (111) were obtained on m-cut (1010) and a-cut (1120) sapphire orientations, respectively. In-plane directions were extracted from TEM analysis on all the samples. Atomic force microscopy revealed fairly smooth MgO films on sapphire, varying from 0.35 nm average roughness for the MgO film on the m-cut substrate to 0.80 nm on the r-cut substrate.