Reduction in the feature sizes of electronic chips is forcing a commensurate decrease inthe sizes of the various structures in packaging so that the assumption that the materials of the structures have bulk properties is suspect, especially near the interfaces. Historically, packaging has not received research and development as sophisticated as thatof the chip, so a collection of techniques specific to packaging technology has not beendeveloped. The National Institute of Standards and Technology (NIST) has identified the need for and initiated efforts to develop and refine such techniques. This paper will discuss the current NIST program and plans which were developed in conjunction with industry and other government agencies. Initial attention is given to measurements of the electrical, thermal, mechanical, and chemical properties of all types of materials used in the packaging.