Extended abstract of a paper presented at Microscopy and Microanalysis 2009 in Richmond, Virginia, USA, July 26 – July 30, 2009

The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.

The use of Au nanoparticles as catalysts for growth of Si nanowires poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts can be broadened when the need for catalytic precursor dissociation is eliminated. However, the requirements for selective deposition in a gas phase transport -limited regime become stringent. When competing deposition of amorphous Si can bury the particles faster than the incubation time for VLS growth, no nanowire growth will be initiated. We show that the use of a catalyst such as In, already in a liquid form at the growth temperature, is effective. Therefore, the choice of VLS catalysts among the low melting point metals from the III, IV and V groups is suggested.

Rare earth scandate thin films (GdScO3 and DyScO3) were investigated with respect to future high-k applications. They were deposited on (100) silicon substrates using either pulsed laser deposition (PLD) or electron beam evaporation. The investigation of the films was done by means of Rutherford backscattering spectrometry, high-temperature X-ray-diffractometry, X-ray reflectometry, spectroscopic ellipsometry, transmission electron microscopy (TEM) and atomic force microscopy. For the electrical characterization capacitor stacks were prepared. Both materials show very promising characteristics independent from the deposition technique used. The films are stoichiometric and amorphous and exhibit a smooth surface (roughness RMS < 1 Å). The amorphous phase is stable up to 1000°C. The electrical characterization revealed featureless C-V-curves with a small hysteresis. From CET plots (CET = capacitance equivalent thickness) k-values between 20 and 23 could be extracted. The electron beam evaporation produces films with a better homogeneity and a thinner interfacial silicon dioxide and therefore a smaller CET value as confirmed by TEM. The leakage current density of the film with CET = 1.5 nm was as low as 7.7x10-4 A/cm2.

The electrical performance of junctions in SiGe Strain Relaxed Buffers (SRB's) with a strained Si top layer is investigated. Most of the SRB's grown in this experiment use a thin C-doped SiGe layer, which allows to fabricate thin (∼250nm) SRB's with a high relaxation degree. The effects of Threading Dislocation Density (TDD) and C-rich layer depth on the electrical behaviour of n+/p and p+/n junctions are studied. The C atoms in the junction's Space Charge Region (SCR) give rise to defects and induce a noticeable increase in the leakage. The effect of the TDD on the leakage in n+/p junctions is linear over the complete voltage range applied, while for p+/n junctions, only a small effect on leakage is measured at V=1V reverse for TDD's below 1×107cm-2. For low reverse voltages, the current varies more linearly with TDD.

Germanium is because of its intrinsically higher mobility than Si, currently under consideration as an alternative approach to improve transistor performance. Germanium oxide, however, is thermodynamically unstable, preventing formation of the gate dielectric by simple oxidation. At present, high-k dielectrics might be considered as an enabling technology as much progress has been made in the deposition of thin high-quality layers.

In this paper, we study the growth and physical properties of HfO2 deposited on Ge by MOCVD, using TDEAH and O2 as precursors, and compare the results to similar layers deposited on silicon substrates. Our results show that the physical properties of MOCVD-deposited HfO2 layers on Ge are very similar to what we have observed in the past for Si. Unfortunately, some of the negative aspects observed for Si, such as diffusion of substrate material in the high-k layer, a low density for thinner layers, or a rough top surface, are also observed for the case of Ge. However, careful surface pretreatments such as NH3 annealing the Ge substrate prior to deposition, can greatly improve the physical properties. An important observation is the very thin interfacial layer between HfO2 and Ge substrate, allowing a more aggressive scaling for Ge.

Solid phase epitaxial regrowth (SPER) has been proven to be highly advantageous for ultra shallow junction formation in advanced technologies. Application of SPER to strained Si/SiGe structures raises the concern that the Ge may out diffuse during the implantation and/or anneal steps and thus reduce the strain in the top silicon layer.

In the present studies we expose 8-30 nm strained silicon layers grown on thin relaxed SiGe-buffers, to implant conditions and anneal cycles, characteristic for formation of the junctions by solid phase epitaxial regrowth and conventional spike activation. The resulting Geredistribution is measured using SIMS. Based on the outdiffused Ge-profiles the Ge-diffusion coefficient has been determined in the temperature range of 800-1100C from which an activation energy of ∼ 3.6 eV can be deduced. Up to 1050 C, 10 min, even a 30 nm strained film remains highly stable and shows only very moderate outdiffusion.

We also have observed a far more efficient, athermal Ge-redistribution process linked to the implantation step itself. This was studied by analysing the Ge-redistribution following an Asimplant (2-15 keV, 5 1014 – 3 1015 at/cm2). It is shown that the energy of the implant species (or more specifically the position of the damage distribution function relative to the Ge-edge) plays a determining factor with respect to the Ge-migration. For implants whereby the damage distribution overlaps with the Ge-edge, a very efficient transport of the Ge is observed, even prior to any anneal cycle. The migration is entirely correlated with the collision cascade and the resulting (forward!) Ge-recoil distribution. The scaling with dose for a given energy links the observed Ge-profile with a broadening mechanism related to the number of atom displacements induced in the sample within the vicinity of the Si-SiGe-transition.

Strain relaxed Si1−xGex layers are attractive virtual substrates for the epitaxial growth of strained Si. Tensile strained Si has attracted a lot of attention due its superior electronic properties. In this study, the strain relaxation of pseudomorphic Si1−xGex layers grown by chemical vapor deposition (CVD) on Si(100) substrates was investigated after He+ ion implantation and thermal annealing. The implantation induced defects underneath the SiGe/Si interface promote strain relaxation during annealing via preferred nucleation of dislocation loops which form misfit dislocations at the interface to the substrate. The amount of strain relaxation as well as the final threading dislocation density depend on the implantation dose and energy. Si1−xGex layers with thicknesses between 75 and 420 nm and Ge concentrations between 19 and 29 at% were investigated. The strain relaxation strongly depends on the layer thickness. Typically the structures show ≈70 % strain relaxation and threading dislocation densities in the low 106 cm−2 range. AFM investigations proved excellent surface morphology with an rms roughness of 0.6 nm. The samples were investigated by Rutherford backscattering spectrometry, ion channeling, transmission electron microscopy and atomic force microscopy.

Germanium is because of its intrinsically higher mobility than Si, currently under consideration as an alternative approach to improve transistor performance. Germanium oxide, however, is thermodynamically unstable, preventing formation of the gate dielectric by simple oxidation. At present, high-k dielectrics might be considered as an enabling technology as much progress has been made in the deposition of thin high-quality layers.

In this paper, we study the growth and physical properties of HfO2 deposited on Ge by MOCVD, using TDEAH and O2 as precursors, and compare the results to similar layers deposited on silicon substrates. Our results show that the physical properties of MOCVDdeposited HfO2 layers on Ge are very similar to what we have observed in the past for Si. Unfortunately, some of the negative aspects observed for Si, such as diffusion of substrate material in the high-k layer, a low density for thinner layers, or a rough top surface, are also observed for the case of Ge. However, careful surface pretreatments such as NH3 annealing the Ge substrate prior to deposition, can greatly improve the physical properties. An important observation is the very thin interfacial layer between HfO2 and Ge substrate, allowing a more aggressive scaling for Ge.

In advanced CMOS technology nodes one may achieve further enhancement of device performance by carrier mobility modification in the transistor channel. The carrier mobility enhancement can be realized by formation of strained silicon layers on a Si1−xGex strain relaxed buffer. Formation of source and drain extensions on such structures need to satisfy one additional requirement, the formation process, including the activation related thermal budget should not relax the strain in the channel. In this paper we separately investigate the role of amorphization during implantation, different doping impurities and thermal budget on the junction and the transistor channel regions properties. Two approaches of dopant activation are discussed: low temperature solid phase epitaxial regrowth and high temperature conventional spike.

Tensile strained Si on SiGe Strain Relaxed Buffers (SRB) is an interesting candidate to increase both electron and hole mobility which results in improved device performance. Most of this work was/is based on thick (several μm), step-graded SRBs with or without Chemical Mechanical Polishing (CMP) planarisation. This approach bears several disadvantages such as issues with STI formation in the thick SiGe structure, and considerable self-heating effects due to the lower thermal conductivity of the SiGe material. Further, pMOS improvement requires SRBs with high Ge contents (> 30 %), which complicates device fabrication even more. To overcome these issues, we developed a new and cost efficient type of thin SRB (∼200 nm). The concept is based on the introduction of a thin carbon-containing layer during growth of a constant composition SiGe layer. The process relies on standard Chemical Vapor Deposition epitaxial technology without need for CMP. It is designed to allow both non-selective growth on blanket wafers and selective growth in the active area of structured wafers with Shallow Trench Isolation (STI). The selective epitaxial process for strained Si on thin SRBs proposed here, allows relatively simple and cost-effective fabrication of strained Si layers on existing STI structures without any process modification. Further, it offers a very flexible fabrication scheme to independently improve nMOS and pMOS devices. The SRB quality is comparable to the best reported in literature so far, with 70 % and 53 % mobility enhancements for long channel nMOSFETs on 22 % Ge SRBs grown on blanket and STI patterned wafers, respectively.

Junctions were formed in thin SiGe/strained Si substrates with a thickness of 250-350 nm to assess the effect of different buffer layer parameters (bandgap, dislocations, thickness) on the junction leakage density that can be expected in MOSFET devices. The implantations used are standard well, channel and Highly Doped Drain (HDD) implants. Both p+/n and n+/p junctions were evaluated. The total thickness of the buffer layers was varied to compare the effect of different structural layers on the diode leakage. This investigation shows that the effect of an increased defect density is dominant at room temperature for the strained Si samples, resulting in 4-5 orders of magnitude increase in leakage. However, there is a different gradation in leakage dependence for thick and thin buffer layers, especially at higher temperatures.

Because of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.

Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).

Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

In the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

Thermal stability of amorphous phases in various high-k layers (Al2O3, ZrO2, HfO2, ZrAlOx, HfAlOx and HfSiOx) and the phase transformation of crystalline ZrO2 and HfO2 were studied experimentally, as functions of surface preparation, deposition conditions, material composition and post deposition thermal treatment. It is found that pure ZrO2 and HfO2 show relatively low crystallization onset temperatures. The crystalline ZrO2 or HfO2 phases are tetragonal or monoclinic, depending on the layer thickness. The phase transformation of metastable t-phase into stable m-phase has been observed in ZrO2 and HfO2. Crystallization behavior of Al2O3 depends on the surface preparation of the substrate. ALCVD grown Al2O3 layers on an oxide-based surface remain amorphous after 1100°C spike annealing, while those on HF-last surface crystallize at temperatures around 800°C. Alloying Al2O3 into ZrO2 and HfO2 can improve their resistance to crystallization under thermal exposure. The kinetics of the crystallization in the alloys can be described by linear TTT curves. Hf-aluminates show better thermal stability than Zr-aluminates. A defect model relative to the phase transformation is discussed, based on the above observations.

Scaled HfAlxOy/SiO2 stacks down to 1.5 nm EOT have been achieved. Although the addition of Al to the HfO2 matrix can be beneficial, it is observed that the benefit of using a Hf-aluminate is compromised if the film has a high Al-content. This is observed in terms of a dielectric constant close to that of pure Al2O3 (∼ 9) and a large amount of negative fixed charge in the film (∼ 1012 cm-2). Using oxygen post deposition anneals we have been able to reduce flatband voltage shifts associated with fixed charge as well as CV hysteresis. In terms of scaling, the benefit of using a high-k material is compromised if a SiO2 layer is also present in the gate stack. Therefore, it is necessary to perform an O2 PDA at moderate temperatures or in low O2 partial pressures in order to control the thickness of the interfacial oxide layer.

Targeting very thin equivalent oxides (<1 nm) requires the deposition of (very) thin dielectrica onto silicon surfaces with minimal interfacial oxide. Typically, high-k dielectric layers are deposited using ALD or MOCVD with, at present, a prime emphasis on Hf-based high-k dielectrics, either as pure HfO2, as silicate or mixed with Al2O3. In some cases nitrogen is added to improve the high-temperature stability. Depending on the deposition conditions ALD as well as MOCVD show serious deficiencies in terms of film closure and material density for ultra thin (<3 nm) films. Various surface preparation methods and deposition conditions are used to improve the film quality. Detailed studies on the film growth and its evolution requires the use of many analytical methods such as Rutherford Backscattering Spectrometry, Low Energy Ion Scattering, Time-of-flight SIMS, (spectroscopic) ellipsometry and X-ray photoelectron spectroscopy. When trying to correlate the results in terms of film thickness, apparent discrepancies can be observed which relate to non-homogeneous growth and reduced material density.

A fast screening technique is used to study the ALD HfO2 growth behavior on different types of starting surfaces (H-passivated, chemical oxide, thermal oxide). The amount of Hf deposited at the early stages of the ALD process is measured by means of RBS. The HfO2 film quality on different starting surfaces is examined with ToFSIMS. The results suggest an island growth mechanism on a H-terminated starting surface: nucleation, development of separated nuclei and flattening. It is shown that ALD growth starts faster if –OH groups are present on the surface. A remote H2 plasma surface pre-treatment at room temperature is also studied. The influence of the plasma exposure time and number of water pulses prior to HfO2 deposition was examined. The H2 plasma surface pre-treatment can be considered as a promising candidate for sub 1 nm EOT performance.

This paper discusses metal organic chemical vapor deposited (MOCVD) HfO2 layers using tetrakis(diethylamido)hafnium (TDEAH) as precursor. We have studied the influence of the starting surface and deposition temperature on the growth kinetics and physical properties of the HfO2 layers. Important characteristics such as crystalline state, density, and organic contamination in the layers were found to be dependent on these parameters.

Typical for this deposition process is the formation of an interfacial layer underneath the high-k layer. Its composition and thickness, affecting scaling of the equivalent oxide thickness, are shown to be closely related to the HfO2 process parameters mentioned above.

Finally, we will show electrical results for HfO2/polySi gate stacks indicating the effect for deposition temperature.

Hafnium-based dielectrics are under wide consideration for high-K gate dielectric applications. Since the gate electrode typically used in CMOS integration consists of polysilicon with n- or p-type dopants, compatibility of the HfO2 layer with the polySi deposition and dopant activation steps is critical. Capacitors were fabricated with HfO2 films deposited by ALD and MOCVD, and using polysilicon gate electrodes deposited by CVD processes. These devices showed leakage failures with yields that were observed to depend on the area, dielectric thickness and annealing conditions during the process. Investigation of the root cause of these leakage failures suggested that the leakage failures may be caused by a defect-related mechanism. The implication of this is that the leakage occurs at localized ‘defect’ sites rather than broadly through the HfO2 layer. Emission microscopy analysis and physical characterization of the HfO2 film were used to corroborate the proposed model. Defect density was observed to be strongly dependent on the processing of the dielectric film. In order to make Hf-based dielectric stacks compatible with polysilicon for conventional CMOS transistor integration with acceptable yield, further postdeposition treatment may be necessary to eliminate or cure the defects.