Supplemental food from anthropogenic sources is a source of conflict with humans for many wildlife species. Food-seeking behaviours by black bears Ursus americanus and brown bears Ursus arctos can lead to property damage, human injury and mortality of the offending bears. Such conflicts are a well-known conservation management issue wherever people live in bear habitats. In contrast, the use of anthropogenic foods by the polar bear Ursus maritimus is less common historically but is a growing conservation and management issue across the Arctic. Here we present six case studies that illustrate how negative food-related interactions between humans and polar bears can become either chronic or ephemeral and unpredictable. Our examination suggests that attractants are an increasing problem, exacerbated by climate change-driven sea-ice losses that cause increased use of terrestrial habitats by bears. Growing human populations and increased human visitation increase the likelihood of human–polar bear conflict. Efforts to reduce food conditioning in polar bears include attractant management, proactive planning and adequate resources for northern communities to reduce conflicts and improve human safety. Permanent removal of unsecured sources of nutrition, to reduce food conditioning, should begin immediately at the local level as this will help to reduce polar bear mortality.

Many new electronic systems require very high-density packaging to meet system volume and weight constraints. The Chip Scale Package (CSP) is often used to meet this need. However, the limited commercial availability of die in CSP form frequently drives system designers to pursue custom CSP fabrication. Long lead times and manufacturers' reluctance to run small batches typically limit the use of custom CSPs to high volume applications. This paper presents an approach for the rapid prototype of Low Temperature Co-fired Ceramic (LTCC) CSPs.

Integral to the approach is the concept of using a small family of generic substrate designs to build a large variety of CSPs. The generic substrates may be fabricated and kept on hand until a CSP application need arises. When it does, a 12-to-16-week industry-typical lead time does not apply; the CSP may be fabricated rapidly, on site. Fabrication consists of simply singulating the substrate, populating the solder ball pads, mounting and wire bonding the die, encapsulating the substrate surface, and laser marking the assembly. The lead time may be slashed from several months to just a few days.

The family of substrate designs will be described. The substrates, with gold-based interconnects, have standard JEDEC Ball Grid Array (BGA) footprints of either 0.8 mm or 1.0 mm pitch. Substrates have a top surface metallization scheme of either a large central die bond pad surrounded by a number of peripheral bond sites for wire bonds, or a blanket metallization layer that may be patterned, via photolithography, to accommodate a specific application at the time of need. The die pad design is used for CSPs with a single die, while the blanket metallization design is patterned for hybrid or multi-die applications. The design approach, custom photopatterning and gold etch, and assembly processes are presented.

LTCC substrates for fine pitch (1.0 mm and 0.8 mm) CSP applications have been designed, fabricated, and assembled. The assembly process, including ball grid array (BGA) solder ball attach, die mount, wire bond, and glob top is described. The material and physical design interaction issues that emerged during development are discussed.

The initial CSP design was conventional, with co-fired yellow gold (Au) vias and capture pads and post-fired solderable gold (PtPdAu) pads for solder ball attachment. Because LTCC tape shrinks during co-fire, solder pads were applied post co-fire to ensure proper mating with existing test fixtures and to provide the best alignment relative to the CSP body. Solder pad to capture pad misalignment was visible following solder pad firing. After CSP attachment to a test board, electrical tests revealed opens. Investigation led to the following conclusions. The decreased solder pad diameter necessary to accommodate the fine pitch design was significant relative to the area allocated for the underlying via and capture pad. Misalignment that would have been hidden under larger solder pads was exposed. Even when the capture pad surface was not visibly exposed, the offset solder pad meant less material between the capture pad and the solder ball, less of a barrier to solder leaching. Solder leaching into the yellow gold, observed after CSP removal from the test board, was the cause of the electrical disconnects. In the second design, the capture pad was eliminated in order to discourage leaching by reducing the volume of yellow gold available to alloy with the solder pad during co-fire. Reflow operations still resulted in leached solder pads. A third design replaced the first-layer via yellow gold with a solderable gold. This design proved to be robust.

While developing designs and fabricating these prototypes, it was noted that all ball failures consistently occurred between the solder pad and the LTCC substrate. To investigate adhesion using different metallizations, shear tests were performed on LTCC substrates with either post-fired solder pads or co-fired pads. To investigate how the substrate material affects adhesion, alumina CSPs were also sheared. Shear test results are presented.

Mechanical prototypes of a silicon interposer device, having high-aspect ratio straight walls, were required for experiments to qualify various packaging assembly options. The ideal solution would yield expendable, quickly made, and relatively inexpensive replica parts.

This need led to the investigation of micromachining of silicon via laser ablation. We sought to optimize the results by varying several parameters, the most influential of which was shown to be laser wavelength. Silicon wafers of thickness 500 νm were machined using laser wavelengths of 10,600 nm, 1064 nm, and 355 nm. As was predicted according to the theoretical silicon absorption profile, the best results were obtained using 355 nm wavelength light from an ultraviolet laser source. Several post-machining cleaning routines, to remove melted silicon debris, were evaluated as well. Pictorial results of both laser processing and cleaning are shown and discussed.

ICP was concurrently investigated as a viable alternative to laser machining. These cuts were markedly cleaner and straighter than those induced by laser; additionally, cut features were more well defined. Pictorial results are compared and contrasted with those of laser ablation.

Cost and time are traded for quality when choosing between laser ablation and ICP etch. Therefore, process choice should be application-dependent. For wafers with moderately complex cutout features, laser micromachining is significantly lower in cost and manufacturing time. However, the laser process does produce residual thermal stress surrounding the cut region, machined edges are relatively rough, and fine features are more difficult to produce. Laser ablation is an attractive manufacturing option for quick-turnaround prototyping as well as high-volume production; ICP is better suited to producing high-definition parts without potential for thermal stress damage.