In this paper, the electrical properties of bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by NiSi2 seed-induced lateral crystallization (SILC) and its applications are presented. Sequential lateral solidification (SLS), which is one of crystallization methods, is known to have poor electrical properties of TFTs with BG structures due to problems induced by laser. Therefore, the laser method cannot be used to well-developed production line of amorphous-Si (a-Si) TFT, resulting in large initial investment cost to change fabrication procedures. On the other hand, the BG poly-Si TFT by SILC (SILC-BGPS TFT) has basically compatible process flows with that of the a-Si TFT. The SILC-BGPS TFT exhibited threshold voltage of -3.9 V, steep subthreshold slope of 130 mV/dec, a high field-effect mobility of 129 cm2/Vs , and I on /I off ratio of ∼106.

A single-grained Pb(Zr,Ti)O3 (PZT) was successfully grown for the gate dielectric of polycrystalline-silicon (poly-Si) thin-film transistor (TFT). The total structure was MoW/PZT/HfO2/poly-Si/glass. The giant single-grained PZT was obtained by controlling the artificial nucleation formed by Pt dots in a desirable location and enlarging the nucleated seed until it covers the poly-Si channel. The single-grained diameter size was 40 μm with a (100) dominated texture. The poly-Si memory device with single-grained PZT showed an excellent ferroelectric, electrical and reliability properties comparing with poly-Si memory device with poly-grained PZT. Moreover, eliminating the grain boundary in PZT film showed the fatigue and retention characteristics with only 1.1 % after 1013 cycles and 22 % after 1 month, respectively.

In this paper, a novel annealing method, scanning-rapid thermal annealing (RTA), for the selectively nucleated lateral crystallization (SNLC) of Pb(Zr,Ti)O3 (PZT) thin films is discussed. The effects of lamp power and scan speed on the SNLC were investigated. It was found that scanning-RTA was very effective method for SNLC in reducing the process time and preventing undesirable nucleation at other than pre-determined positions.

Selective nucleation and lateral growing method have been developed for high quality ferroelectric PZT(65/35) thin films using perovskite-phase PZT island seed. The PZT films on PZT seed island were transformed into the perovskite phase at temperatures as low as 540°C, which is 150°C lower than compared to that of PZT thin films deposited on Pt films. The temperature difference enables lateral growth without undesirable random nucleation. Maximum grain sizes of the perovskite-phase PZT films were determined by the annealing temperature. The PZT thin films show a leakage current density of 8×10−8 A/cm2, breakdown field of 1240 kV/cm, saturation polarization of 42 μC/cm2, and remanent polarization of 30 μC/cm2, whose values were maintained up to 2×1011 cycles. In this study, we show that when there was no grain boundary in the area measured, degradation such as fatigue and retention was not observed even with Pt electrodes. So the main source of degradation is the grain boundary in the PZT thin films.

The effects of grain boundaries on the characteristics of the PZT thin films using single-grained PZT array by selective nucleation and growth method were investigated by locating the upper Pt electrode of 8 μm× 8 μm sized square directly on the single grains, 1 grain boundary and 4 grain boundaries in a controlled manner. It turned out that when there was no grain boundary, the best ferroelectric and electrical performance were obtained as expected. However, serious degradation was observed in polarization, leakage current, breakdown field and fatigue characteristics when grain boundary was contained in the area measured. This is the first qualitative investigation about the effects of the grain boundaries on the ferroelectric and electrical performance of the PZT thin films. It was found that degradation of the PZT thin films was accelerated with increasing the length of the grain boundaries within the top electrode and the main source of degradation in PZT thin films is grain boundary.

BST thin films have been fabricated by RF magnetron sputtering onto Ir layer as a bottom electrode. When the substrate temperature was maintained at 600 °C during deposition, BST films deposited at that temperature showed very small oxide equivalent thickness of 0.36nm as well as very low leakage current density of about 10−8A/cm2 at 1.5V. But as substrate temperature was increased to 700 °C in order to obtain high dielectric constant, oxide equivalent thickness exhibited very low value of about 0.3nm, however, leakage current density drastically increased to 10−4/cm2. BST thin films were fabricated by two step process, which consists of bottom layer deposited at high substrate temperature of 700 °C and top layer deposited at low substrate temperature. In the case of BST thin films which are composed of 20nm thick bottom layer deposited at 700 °C and 30nm thick top layer deposited at 500 °C, we obtained very small oxide equivalent thickness of 0.31nm and low leakage current density of 4 × 10−8 A/cm2. at 1.5V.

[Cu(20Å)/NiFe(7Å)/Ni(6Å)/NiFe(7Å)]10Cu(50Å) multilayers were deposited on 4 ° tilt-cut Si(lll) using 3-gun rf magnetron sputtering system. An in-plane uniaxial magnetic anisotropy was found and the uniaxial magnetic anisotropy constant was about 3×104 erg/cm3. The multilayers on non tilt-cut Si(lll) with Cu underlayer did not show any anisotropy. The crystal structure of the multilayer on 4 ° tilt-cut Si(111) was studied using TEM work and the magnetic anisotropy is originated from the growth of (110) preferred orientation of the multilayer. When other material such as Ni or NiFe was used as an underlayer for the multilayer, the magnetic anisotropy disappeared and the crystal structure was (111). The multilayer without underlayer did not show any magnetic anisotropy either. It is thought that Cu underlayer was grown with (110) orientation on 4 ° tilt-cut Si(111) through the ledges in Si wafer and worked as a template for the growth of the multilayer.

An aluminum thin film for ultra large scale integrated circuits(ULSI) metalization has been formed by PACVD using DMEAA(Dimethylethylamine alane) as a precursor. The selectivity was lost but the conformal step coverage was still maintained when the hydrogen plasma was added to conventional CVD process so that perfectly planarized metalization could be obtained.

Comparing to thermal CVD, the reflectivity as well as the resistivity could be much improved especially when the film was deposited on SiO2. The deposition rate and the resistivity of PACVD Al thin films deposited on various substrates such as Si, TiN and SiO2 were compared with those of thermal CVD Al thin films.

High performance poly-Si thin film transistors were fabricated by using a new crystallization method, Metal-Induced Lateral Crystallization (MILC). The process temperature was kept below 500°C throughout the fabrication. After the gate definition, thin nickel films were deposited on top of the TFT's without an additional mask, and with a one-step annealing at 500°C, the activation of the dopants in source/drain/gate a-Si films was achieved simultaneously with the crystallization of the a-Si films in the channel area. Even without a post-hydrogenation passivation, mobilities of the MILC TFT's were measured to be as high as 120cm2/Vs and 90cm2/Vs for n-channel and p-channel, respectively. These values are much higher than those of the poly-Si TFT's fabricated by conventional solid-phase crystallization at around 6001C.

A new oxidation process of the poly Silicon thin films has been demonstrated, where the amorphous silicon thin film was oxidized by ECR plasma at room temperature and then crystallized at 600°C for 30hrs(pre-oxidation). For comparison, amorphous silicon thin film was oxidized after crystallization(post-oxidation). The interface roughness turned out to be only 3Å in case of the pre-oxidation process, while the post-oxidation showed about 8Å of the interface roughness. The pre-oxidized TFT showed the constant mobility at high gate voltages, the post-oxidized TFT showed serious degradation of the mobility at high gate voltages.

Single crystalline silicon thin films were formed on a transparent quartz substrate by zone melting recrystallization for the application of flat panel display. The recrystallized film shows a perfect (100) texture and the main defects are subgrainboundaries. High residual tensile stress, which can cause the film cracking, can be successfully eliminated by post-annealing. The nchannel thin film transistors fabricated on a recrystallized film showed excellent device characteristics: carrier mobility ˜ 420cm2/Vsec, subthreshold slope ˜ 100mV/dec and off-state leakage current < 0.2pA.

Poly-Si TFT’s were fabricated on the glass substrate by the Metal Induced Lateral Crystallization(MILC). Before deposition of the active a-Si thin films(1000 Å), the glass substrate was pretreated in three different ways such as oxidation of a-Si(100 Å), oxide buffer layer deposition(1000 Å), and ion mass doping of the glass substrates. The leakage current at reverse bias could be reduced by one order of magnitude by the substrate pretreatment. Field effect mobility of n-channel TFT’s was 108cm2/Vsec, subthreshold slope and on/off current ratio were 0.7 V/dec. and about 106, respectively.

Basic mechanisms for both Ni- and Pd-metal induced lateral crystallization (MILC) are investigated. For both cases, tiny silicides were formed under the metal deposited area, and propagated toward amorphous Si films leaving crystallized Si behind at temperatures as low as 500 °C. Ni-MILC was influenced by Pd such that the lateral crystallization rate was enhanced, and the temperature for the lateral crystallization was lowered to 450 °C. Through TEM analysis and external stress experiments, it was found that the enhancement of the lateral crystallization rate was closely related to the compressive stress generated by the formation of nearby Pd2Si.

PZT (PbxZr0.4Ti0.6O3) thin filmswere prepared by reactive co-sputtering and annealed by RTA (Rapid ThermalAnnealing). Transformation kinetics and effect of Pb content on thetransformation were intensively studied using EMA (Effective MediumApproximation). It has been found that depending on Pb content as well asRTA temperature, the crystal structure of PZT films changed greatly. Itturned out that the transformation temperature for the perovskite phase canbe lowered and the width of transition temperature region was reduced byincreasing Pb content in the films. Dependence of transformation path on thePb content has been studied.

Silicon thin films were deposited by Electron Cyclotron Resonance PECVDusing silane as a source gas at room temperature. Deposited films werecrystallized either by conventional furnace annealing(FA) or by rapidthermal annealing (RTA) process. The films deposited on SiO2/Siwafer substrates were Amorphous or microcrystalline depending on themicrowave power. Deposited films were annealed at 600TC in a furnace. Asexpected, higher crystallinity was obtained in the case of the Amorphousfilms than the microcrystalline films after 7.5 hours annealing. It took 15hours at 600δC for the Amorphous films to reach their maximum crystallinityin case of FA, but it only took 1 second at 900 δC for RTA. In addition, itwas shown that RTA can be applied to the rapid crystallization of Amorphoussilicon thin films deposited on a fused quartz substrate utilizing a newfilm structure.

Microcrystalline silicon films were formed at room temperature without hydrogen dilution by ECR PECVD. Microwave power more than 400 W was necessary to get crystalline films and the crystallinity increased with the power thereafter. Addition of hydrogen and argon enhanced the crystalline phase formation and the deposition rate, the reason of which was found that hydrogen etched silicon films and argon addition drastically increased the etch rate. Annealing of the films showed that microcrystalline silicon films formed by ECR PECVD have a small fraction of amorphous phase. TFT's using silicon nitride and doped/undoped microcrystalline silicon films were fabricatedd with whole processes at room temperature.

Silicon nitride thin films were deposited on single crystalline silicon substrates at room temperature by ECR PECVD with SiH4 and N2 as source gases and the electrical properties were analyzed. The dominant conduction mechanism in a high field was Poole-Frenkel emission. A ledge in I-V curve was observed in the first voltage ramp and it was found to originate from the field reduction at the injecting electrode due to the charge trapped in deep traps in the film. It also turned out that the ledge is a characteristic of monopolar conduction. A new interpretation of the current at low field — tunneling into trap states — was proposed and the current variations according to the field and temperature could be well explained.