Boron doped CVD diamond has been extensively studied in bulk form but little has been published regarding the effects that the initial seeding and growth conditions can have on the characteristics of the initial layer of diamond. This can have a dramatic effect on the performance of the film in applications ranging from AFM probe tips to electrodes used for water purification and other applications. This paper will examine how initial growth conditions and seeding methods can affect the film interface characteristics of doped diamond grown in hot filament CVD reactors.

The use of carbon nanotubes (CNT) as interconnects in future integrated circuits (IC) is being considered as a replacement for copper. As this research needs also innovative metrology solutions, we have developed a combined approach for the plane-view analysis of CNT integrated in contact holes where transmission electron microscopy (TEM) enables the quantitative measurement of density and structure of the CNT and where scanning spreading resistance microscopy (SSRM) is used to electrically map the distribution of the CNT. This paper explains the used methodologies in detail and presents results from 300 nm diameter contact holes filled with CNT of 8-12 nm in diameter and a density of about 2 x 1011 cm-2.

This work aims at attaining a more complete understanding of the principles governing resistive contrast imaging (RCI) of copper/low-k interconnects used for dielectric breakdown studies in a nanoprober scanning electron microscope (SEM) system. RCI is employed in such in situ dielectric breakdown studies to facilitate the localization of interconnect defect sites related to various stages in the degradation process of the low-k dielectric material. This work shows that RCI is suitable for detecting high-resistance sites, like opens, in copper/low-k interconnects. Moreover, RCI demonstrates potential in locating defects that lie deep in the test structure and are, thus, not detectable by SEM. A model is also proposed to explain the formation of RCI images of specific interconnect test structures with complex layout.

The successful implementation of silicon nanowire (NW)-based tunnel-field effect transistors (TFET) critically depends on gaining a clear insight into the quantitative carrier distribution inside such devices. Therefore, we have developed a method based on scanning spreading resistance microscopy (SSRM) which allows quantitative two-dimensional (2D) carrier profiling of fully integrated NW-based TFETs with 2 nm spatial resolution. The keys in our process are optimized NW cleaving and polishing steps, in-house fabricated diamond tips with ultra-high resolution, measurements in high-vacuum and a dedicated calibration procedure accounting for dopant dependant carrier mobilities.

Conductive diamond films are essential for electronic applications of diamond but there is still a poor understanding of the effects that growth conditions, grain size and film thickness have on the ultimate conductivity of the film. One of the unique advantages of hot filament diamond is the ability to grow both MCD and NCD films to moderate thicknesses over large areas with little or no change in morphological characteristics such as grain size. In addition the grain size of the film can be altered without the necessity of adding additional gases to the process or unduly increasing the carbon to hydrogen ratio. This gives us an opportunity to investigate electrical conductivity as a function of grain size and thickness within a simple methane, hydrogen, and boron chemical environment over areas which are large enough to support significant production levels of MEMS and other diamond based electronics. In this study the boron source was selected to be trimethyl boron gas to avoid any source of oxygen which could alter the growth conditions and to guarantee that any byproducts of the dopant would be primarily methyl based. The films were grown to various thicknesses up to 5 micrometers and grain sizes from NCD to full MCD at all thicknesses. This paper explores the effects of both grain size and film thickness on the electrical conductivity of the film as well as the absolute doping levels within the film.

In order to continuously improve the performances of microelectronics devices through scaling, SiO2 is being replaced by high-k materials as gate dielectric; metal gates are replacing poly-Si. This leads to increasingly more complex stacks. For future generations, the replacement of Si as a substrate by Ge and/or III/V material is also considered. This also increases the demand on the metrology tools as a thorough characterization, including composition and thickness is thus needed. Many different techniques exist for composition analysis. They usually require however large area for the analysis, complex instrumentation and can be time consuming. EDS (Energy Dispersive Spectroscopy) when coupled to Scanning Electron Microscopy (SEM) has the potential to allow fast analysis on small scale areas.

In this work, we evaluate the possibilities of EDS for thin film analysis based on an intercomparison of composition analysis with different techniques. We show that using proper modeling, high quality quantitative composition and thickness of multilayers can be achieved.

The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.

The characterization of doped regions inside silicon nanowire structures poses a challenge which must be overcome if these structures are to be incorporated into future electronic devices. Precise cross-sectioning of the nanowire along its longitudinal axis is required, followed by two-dimensional electrical measurements with nanometer spatial resolution. The authors have developed an approach to cross-section silicon nanowires and to characterize them by scanning spreading resistance microscopy (SSRM). This paper describes a cleaving- and polishing-based cross-sectioning method for silicon nanowires. High resolution SSRM measurements are demonstrated for epitaxially grown and etched silicon nanowires.

X-ray photoelectron spectroscopy (XPS) has become increasingly important over the past few years for supporting the development of ultra-thin layers for high-k metal gates. As the analysis depth of XPS is however limited to about 5-7 nm, it would be extremely useful if the analysis could be carried out from the backside using standard silicon wafers. This approach puts extreme requirements on the sample preparation as hundreds of micrometers of bulk silicon have to be removed and one has to stop with nanometer precision when reaching the interface to the ultra-thin layer stack. Therefore, we have developed dedicated procedures for preparing and analyzing samples for backside XPS analysis. This paper presents the developed approach with a focus on sample preparation using plan-parallel polishing, endpoint detection by interference fringes, and selective wet etching. First angle-resolved XPS (ARXPS) analysis results of metal gate stacks demonstrate the power of such backside analysis.

The potential use of carbon nanotubes (CNT) as interconnects requires also new characterization approaches as the existing ones are optimized for three-dimensional materials and do not work for inherently one-dimensional structures like CNTs. Therefore, we have developed a so-called pick-and-place process which allows to remove an individual CNT from a specific site and to place it at another location for further analysis. The approach is based on nanomanipulation combined with scanning electron microscopy (SEM). This paper presents the pick-and-place concept and explains the different steps required for its successful application. We further demonstrate its power by characterizing individual CNTs using transmission electron microscopy (TEM) and atomic force microscopy (AFM). The developed pick-and-place approach overcomes the challenge of site-specific analysis of CNT interconnects and strongly facilitates the routine analysis of CNTs.