This paper describes a reconstruction method for atom probe tomography based on a bottom-up approach accounting for (i) the final tip morphology (which is frequently induced by inhomogeneous evaporation probabilities across the tip surface due to laser absorption, heat diffusion effects, and inhomogeneous material properties), (ii) the limited (and changing) field of view, and (iii) the detector efficiency. The reconstruction starts from the final tip morphology and reverses the evaporation sequence through the pseudo-deposition of defined small reconstruction volumes, which are then stacked together to create the full three-dimensional (3D) tip. The subdivision in small reconstruction volumes allows the scheme to account for the changing tip shape and field of view as evaporation proceeds. Atoms within the same small reconstruction volume are reconstructed at once by placing atoms back onto their possible lattice sites through a trajectory-matching process involving simulated and experimental hit maps. As the ejected ion trajectories are simulated using detailed electrostatic modeling inside the chamber, no simplifications have been imposed on the shape of the trajectories, projection laws, or tip surface. We demonstrate the superior performance of our approach over the conventional reconstruction method (Bas) for an asymmetrical tip shape.

Reliable spatially resolved compositional analysis through atom probe tomography requires an accurate placement of the detected ions within the three-dimensional reconstruction. Unfortunately, for heterogeneous systems, traditional reconstruction protocols are prone to position some ions incorrectly. This stems from the use of simplified projection laws which treat the emitter apex as a spherical cap, although the actual shape may be far more complex. For instance, sampled materials with compositional heterogeneities are known to develop local variations in curvature across the emitter due to their material phase specific evaporation fields. This work provides three pivotal precursors to improve the spatial accuracy of the reconstructed volume in such cases. First, we show scanning probe microscopy enables the determination of the local curvature of heterogeneous emitters, thus providing the essential information for a more advanced reconstruction considering the actual shape. Second, we demonstrate the cyclability between scanning probe characterization and atom probe analysis. This is a key ingredient of more advanced reconstruction protocols whereby the characterization of the emitter topography is executed at multiple stages of the atom probe analysis. Third, we show advances in the development of an electrostatically driven reconstruction protocol which are expected to enable reconstruction based on experimental tip shapes.

Boron doped CVD diamond has been extensively studied in bulk form but little has been published regarding the effects that the initial seeding and growth conditions can have on the characteristics of the initial layer of diamond. This can have a dramatic effect on the performance of the film in applications ranging from AFM probe tips to electrodes used for water purification and other applications. This paper will examine how initial growth conditions and seeding methods can affect the film interface characteristics of doped diamond grown in hot filament CVD reactors.

The use of carbon nanotubes (CNT) as interconnects in future integrated circuits (IC) is being considered as a replacement for copper. As this research needs also innovative metrology solutions, we have developed a combined approach for the plane-view analysis of CNT integrated in contact holes where transmission electron microscopy (TEM) enables the quantitative measurement of density and structure of the CNT and where scanning spreading resistance microscopy (SSRM) is used to electrically map the distribution of the CNT. This paper explains the used methodologies in detail and presents results from 300 nm diameter contact holes filled with CNT of 8-12 nm in diameter and a density of about 2 x 1011 cm-2.

This work aims at attaining a more complete understanding of the principles governing resistive contrast imaging (RCI) of copper/low-k interconnects used for dielectric breakdown studies in a nanoprober scanning electron microscope (SEM) system. RCI is employed in such in situ dielectric breakdown studies to facilitate the localization of interconnect defect sites related to various stages in the degradation process of the low-k dielectric material. This work shows that RCI is suitable for detecting high-resistance sites, like opens, in copper/low-k interconnects. Moreover, RCI demonstrates potential in locating defects that lie deep in the test structure and are, thus, not detectable by SEM. A model is also proposed to explain the formation of RCI images of specific interconnect test structures with complex layout.

The successful implementation of silicon nanowire (NW)-based tunnel-field effect transistors (TFET) critically depends on gaining a clear insight into the quantitative carrier distribution inside such devices. Therefore, we have developed a method based on scanning spreading resistance microscopy (SSRM) which allows quantitative two-dimensional (2D) carrier profiling of fully integrated NW-based TFETs with 2 nm spatial resolution. The keys in our process are optimized NW cleaving and polishing steps, in-house fabricated diamond tips with ultra-high resolution, measurements in high-vacuum and a dedicated calibration procedure accounting for dopant dependant carrier mobilities.

Conductive diamond films are essential for electronic applications of diamond but there is still a poor understanding of the effects that growth conditions, grain size and film thickness have on the ultimate conductivity of the film. One of the unique advantages of hot filament diamond is the ability to grow both MCD and NCD films to moderate thicknesses over large areas with little or no change in morphological characteristics such as grain size. In addition the grain size of the film can be altered without the necessity of adding additional gases to the process or unduly increasing the carbon to hydrogen ratio. This gives us an opportunity to investigate electrical conductivity as a function of grain size and thickness within a simple methane, hydrogen, and boron chemical environment over areas which are large enough to support significant production levels of MEMS and other diamond based electronics. In this study the boron source was selected to be trimethyl boron gas to avoid any source of oxygen which could alter the growth conditions and to guarantee that any byproducts of the dopant would be primarily methyl based. The films were grown to various thicknesses up to 5 micrometers and grain sizes from NCD to full MCD at all thicknesses. This paper explores the effects of both grain size and film thickness on the electrical conductivity of the film as well as the absolute doping levels within the film.

In order to continuously improve the performances of microelectronics devices through scaling, SiO2 is being replaced by high-k materials as gate dielectric; metal gates are replacing poly-Si. This leads to increasingly more complex stacks. For future generations, the replacement of Si as a substrate by Ge and/or III/V material is also considered. This also increases the demand on the metrology tools as a thorough characterization, including composition and thickness is thus needed. Many different techniques exist for composition analysis. They usually require however large area for the analysis, complex instrumentation and can be time consuming. EDS (Energy Dispersive Spectroscopy) when coupled to Scanning Electron Microscopy (SEM) has the potential to allow fast analysis on small scale areas.

In this work, we evaluate the possibilities of EDS for thin film analysis based on an intercomparison of composition analysis with different techniques. We show that using proper modeling, high quality quantitative composition and thickness of multilayers can be achieved.

The characterization of doped regions inside silicon nanowire structures poses a challenge which must be overcome if these structures are to be incorporated into future electronic devices. Precise cross-sectioning of the nanowire along its longitudinal axis is required, followed by two-dimensional electrical measurements with nanometer spatial resolution. The authors have developed an approach to cross-section silicon nanowires and to characterize them by scanning spreading resistance microscopy (SSRM). This paper describes a cleaving- and polishing-based cross-sectioning method for silicon nanowires. High resolution SSRM measurements are demonstrated for epitaxially grown and etched silicon nanowires.

X-ray photoelectron spectroscopy (XPS) has become increasingly important over the past few years for supporting the development of ultra-thin layers for high-k metal gates. As the analysis depth of XPS is however limited to about 5-7 nm, it would be extremely useful if the analysis could be carried out from the backside using standard silicon wafers. This approach puts extreme requirements on the sample preparation as hundreds of micrometers of bulk silicon have to be removed and one has to stop with nanometer precision when reaching the interface to the ultra-thin layer stack. Therefore, we have developed dedicated procedures for preparing and analyzing samples for backside XPS analysis. This paper presents the developed approach with a focus on sample preparation using plan-parallel polishing, endpoint detection by interference fringes, and selective wet etching. First angle-resolved XPS (ARXPS) analysis results of metal gate stacks demonstrate the power of such backside analysis.

Oxides have always been an integral part of semiconductor manufacturing both in front and back-end processing. With the necessary increase in performance, the demand on these oxides has been increasing leading to their (future) replacement by more complex materials, such as high-k's in gate oxide and metal gates. With the increasing material complexity, a thorough characterization of all aspects of these materials is necessary, covering, for instance, surfaces and interfaces, nucleation, growth, atomic structure, …

This article focuses on the characterization of front-end oxides and their interfaces. It shows that detailed information can be achieved by sophisticated experimental techniques such as synchrotron radiation, high energy ERD or AtomProbe but that adequate sample preparation and/or analysis by a combination of more routinely available techniques may achieve similar results. This is shown through the study of three different systems/problems in the gate stack analysis. We will first focus on the determination of substrate surface preparation conditions before deposition and their influence on growth mode and the growth characteristics by different growth techniques (ALD, MOCVD, …). Second, we present the possibilities of compositional depth profiling of thin layers both with nuclear techniques and Angle-Resolved XPS. Finally, we will show that using conventional XPS and a combination of front and back-side analysis, the interface between high-k oxide and metal gates can be investigated. More examples of gate stack characterization can be found elsewhere

The potential use of carbon nanotubes (CNT) as interconnects requires also new characterization approaches as the existing ones are optimized for three-dimensional materials and do not work for inherently one-dimensional structures like CNTs. Therefore, we have developed a so-called pick-and-place process which allows to remove an individual CNT from a specific site and to place it at another location for further analysis. The approach is based on nanomanipulation combined with scanning electron microscopy (SEM). This paper presents the pick-and-place concept and explains the different steps required for its successful application. We further demonstrate its power by characterizing individual CNTs using transmission electron microscopy (TEM) and atomic force microscopy (AFM). The developed pick-and-place approach overcomes the challenge of site-specific analysis of CNT interconnects and strongly facilitates the routine analysis of CNTs.

Laser annealed junctions and advanced ultra shallow junctions are studied in both atomistic modeling and experiments. SIMS and sheet resistance measurement for spike-RTA + Laser annealing show that additional laser annealing after spike-RTA (“+Laser”) improve the dopant activation level without increasing in junction depth. “+Laser” effect become effective in the combination of low spike-RTA temperature and high laser temperature. This effect is significant for As doped layer. Spike-RTA based junction has a limitation in viewpoint of Rs-Xj trade-off. Laser-only annealing is promising candidate to overcome this limitation. Boron diffusion with laser-only annealing is investigated. As atomistic kinetic Monte Carlo modeling show that BnIm complexes and End-of-Range (EOR) defects are formed during sub-millisecond annealing time range. Impact of F co-implant on Boron diffusion and EOR defect evolution during sub-millisecond annealing are also investigated.

Local phenomena like trap assisted tunneling and oxide breakdown (BD) in new high-k gate oxides in advanced MOS devices hinder the acquisition of device requirements stated in the International Technology Roadmap for Semiconductors (ITRS). Conductive Atomic Force Microscopy (C-AFM) visualizes these local phenomena by measuring the local tunneling through the dielectric. In the first part of this work we show that the physical composition of surface protrusions, that are produced at sites electrically stressed with C-AFM and that distort the electrical measurements, is oxidized Si. In the second part, we illustrate that C-AFM measurements become more reliable in high vacuum (1e−5torr) as surface (oxidized Si protrusions) and tip damage is reduced. Finally, we illustrate good agreement between conventional macroscopic electrical measurements and nanometer-scale C-AFM measurements on normal and gate – removed high-k capacitors, respectively. Moreover, to illustrate the strength of the local tunneling technique, we show the possibility of locating BD spots on a high-k capacitor.

Junction formation in FinFET-based 3D-devices is a challenging problem as one targets a complete conformal doping of the source/drain regions in order to produce equal gate-profile overlaps (and thus transistor behavior) on all sides of the fins. Due to the lack of predictive modeling for several of the doping strategies explored (plasma immersion, cluster implants, vapor phase deposition, etc…) it becomes difficult to correctly predict the performance of the devices and hence, accurate 3D-doping profile determination is desired. Although several dopant/carrier profiling methods exist with excellent one- or two-dimensional resolution and properties, there is an urgent need to extend these towards a quantitative three-dimensional geometry. In this work, we use scanning spreading resistance microscopy (SSRM) with dedicated FinFET test structure to obtain three-dimensional information from successive two-dimensional scanning spreading resistance maps. We also assess the validity of our methodology by comparing various sections along the fins which represent the variability due to the processing and measurement procedure.