Logical characterizations of algebraic circuit classes over integral domains

We present an adapted construction of algebraic circuits over the reals introduced by Cucker and Meer to arbitrary inﬁnite integral domains and generalize the AC R and NC R classes for this setting. We give a theorem in the style of Immerman’s theorem which shows that for these adapted formalisms, sets decided by circuits of constant depth and polynomial size are the same as sets deﬁnable by a suitable adaptation of ﬁrst-order logic. Additionally, we discuss a generalization of the guarded predicative logic by Durand, Haak and Vollmer, and we show characterizations for the AC R and NC R hierarchy. Those generalizations apply to the Boolean AC and NC hierarchies as well. Furthermore, we introduce a formalism to be able to compare some of the aforementioned complexity classes with different underlying integral domains.


Introduction
Boolean circuits as a computational model are a fundamental concept in the study of theoretical computer science.Mainly in computational complexity, Boolean circuits play a central part in the analysis of parallel algorithms and the corresponding complexity classes, enabling a finer view and providing new proof methods, especially for subpolynomial complexity classes.An obvious generalization of Boolean circuits is that instead of dealing with truth values as inputs -or the field Z 2 for the algebraically minded -we consider elements from some other algebraic structure.This approach has its roots in the works of Blum, Shub and Smale, whose model of the BSS-machine is able to describe computations over real numbers.Following this, Blum, Shub, Smale and Cucker (Blum et al., 1998) also give a generalization to algebraic circuits over the reals.

Our contribution
In this article, we provide logical characterizations of circuit complexity classes over integral domains.In particular, we define natural extensions of the classical circuit complexity hierarchies AC i and NC i over arbitrary integral domains.The resulting classes are denoted as AC i R and NC i R , respectively.We adapt the framework of metafinite model theory to define various extensions of first-order logic, which capture these new complexity classes.
We establish a Immerman-style theorem stating that FO R = AC 0 R and provide a framework to establish complexity-theoretic comparisons of classes with different underlying integral domains and give examples over which integral domain the AC 0 classes are equal.
We adapt the GPR operator, which Durand, Haak and Vollmer use to provide logical characterizations of AC 1 and NC 1 (Durand et al., 2018) to logics over metafinite structures and extend it to be able to characterize the whole AC R and NC R hierarchies.
Finally, we define a formalism suitable for comparing complexity classes with different underlying integral domains and we show that a hierarchy of sets of complexity classes emerges, such that each set is able to "simulate" the complexity classes from the sets lower in the hierarchy.

Related work
Another model of computation that is commonly known under the name "algebraic circuit" are Valiant circuits (Valiant, 1979), which are the foundational model in the emerging subfields of algebraic and geometric complexity theory.They differ from the model we analyse in this work in the way that we use < gates, which are not available in the Valiant setting.This difference is of complexity-theoretical significance, since for our model, we have that NC i R NC i+1 R (Cucker, 1992) but we have that VNC 2 = VNC 3 = . . .= VP (Bürgisser, 2013) in the Valiant setting for every field, in particular over the reals.

Outline of the paper
We start with an overview of some central concepts from algebra and circuit complexity, which are needed for the definition of our model.We then establish our model of algebraic circuits for arbitrary integral domains and the analogous complexity classes induced by them in analogy to the Boolean case.Afterwards, we give a logical characterization of the presented circuit classes inspired by classical descriptive complexity.However, since our models now have an infinite component, we build on the foundations of metafinite model theory.
We then go on to define first-order logic over R and show that, like in the classical case, we have that AC 0 R = FO R [Arb R ] + SUM R + PROD R .In Section 4, we give logical characterizations of AC i and NC i .The tool of our choice is an adaptation of the guarded predicative logic of Durand et al. (2018).
In Section 5, we discuss connections between AC 0 R classes over different integral domains.

Preliminaries
First, we discuss the theoretical background of this paper.We give the basic definitions and remarks on the notation used in this paper.We denote the set of natural numbers with 0 as N and the set of natural numbers without 0 as N >0 .
Notation 1.In this paper, we will generally use overlined letters (e. g. x) to denote tuples.
As the name suggests, algebraic circuit classes make use of concepts originating from abstract algebra.We assume the reader has basic knowledge of algebra, especially rings, integral domains and fields, polynomials and adjoining elements to rings.For an introduction to abstract algebra, the reader may refer to the books by Aluffi (2009) or Lang (2002).
Our considered rings are always assumed to be a commutative ring with unit.Throughout the paper, whenever not otherwise specified, we use R to denote an infinite integral domain.
Remark 2. In particular, we require that for every r ∈ R the equations r × 0 = 0 0 × r = 0 hold.
Example 3. Popular examples of rings include Z, Q, R and C, as well as sets with adjoined elements like Z where k ∈ N, p = q are primes and j k denotes the kth root of −1, that is i k k = −1.Alternatively, we can adjoin algebraic independent prime root elements with 2 = k and get an analogous construction.
Remark 4. The denotation of R[j k ] resp.Z[j k ] is not unique but the constructions of the circuit over the underlying rings are analogous except for the placeholders for the adjoined numbers.For example, Z 4 can denote Z[j 4 ] = Z[j 4 , j 2 4 , ] or many other rings.Since we only focus on the structure of the tuples, that is the coefficients of adjoint elements, or later the underlying circuits, our short notation for Z k for arbitrary k > 1 is not unique and may differ, for example Z 2 may denote Z[j] or may denote Q.In the context of the placeholder notation, the arithmetic of the specific ring must be clear, if it is important.
We need some ordering < on our integral domain R.In some cases, like R and Z, we have some natural ordering that we want to use.In other cases, like C, we have to construct some ordering.This ordering does not have to be closed under multiplication, and we only have to distinguish different numbers from each other.So an ordering on tuples (z Definition 5. A strict total order on a set S is a binary relation < on S which is irreflexive, transitive and total.
Example 6.For some field F p k for some prime p and a natural number k, we write the finitely many elements in a list and then use the lexicographical on this list.For example, let R = Z 3 .Then, we define < Z 3 as 0 < 1 < 2.
There are multiple possibilities for such a < over the field of complex numbers.Let z = a + bj ∈ C and let < 1 be the lexicographic order on pairs ( √ a 2 + b 2 , a).Furthermore, let < 2 be the lexicographic order on pairs of the form (a, b).Then, both variants are possible since both distinguish different complex numbers.Definition 7. A strict total order < over a ring R induces a sign function as follows: In the following, unless explicitly otherwise specified, the symbol R denotes an infinite integral domain with a strict total order < on R. Most of the rings we consider have a natural ordering.In this case, we omit the ordering symbol.

Algebraic circuits over R
As this work is a generalization of the well established Boolean circuits, some background in circuit complexity is assumed.Standard literature which introduces this topic is the book by Vollmer (1999).The generalization to algebraic circuits over real numbers were first introduced by Cucker (1992).In analogy to them, Barlag and Vollmer defined an unbounded fan-in version of algebraic circuits (Barlag and Vollmer, 2021).Definition 8. We define an algebraic circuit C over an integral domain R with a strict total order <, or R circuit for short, as a directed acyclic graph.It has gates of the following types: Input nodes have indegree 0 and contain the respective input values of the circuit.Constant nodes have indegree 0 and are labelled with elements of R Arithmetic nodes have an arbitrary indegree ≥ 1, bounded by the number of nodes in the circuit and are labelled with either + or ×.Comparison (<) nodes have indegree 2. Output nodes have indegree 1 and contain the output value after the computation of the circuit.
Nodes cannot be predecessors of the same node more than once, and thus, the outdegree of nodes in these algebraic circuits is bounded by the number of gates in the circuit.
During the computation of an algebraic circuit, the arithmetic gates compute their respective functions with the values of their predecessor gates being taken as the function arguments and the comparison gates compute the characteristic function of < in the same way.The values of the output gates at the end of the computation are the result of the computation.
In contrast to the classical setting, where we consider words over an alphabet as inputs, and where languages are thus defined to be subsets of the Kleene closure of the alphabet (in symbols, L ⊆ * ), we consider vectors of integral domain elements as input.In analogy to * , we denote for an integral domain R: With |x|, we denote the length of x, i. e., if x ∈ R k then |x| = k.
Remark 9. We will use the term algebraic circuit to describe circuits in the sense of Blum et al. (1998) rather than arithmetic circuits as for example in Barlag and Vollmer (2021) to distinguish them from arithmetic circuits in the sense of Valiant, see for example (Bürgisser et al., 1997).Valiant circuits are essentially algebraic circuits without sign or comparison gates (Blum et al., 1998, page 350).
Remark 10.In the special case R = Z 2 , the definition above yields exactly the Boolean circuits.
Definition 11.We call the number of gates in a circuit the size of the circuit and the longest path from an input gate to an output gate the depth of the circuit.
Remark 12. Unlike the way algebraic circuits with unbounded fan-in gates were introduced previously (Barlag and Vollmer, 2021), algebraic circuits in this context have comparison gates instead of sign gates.This stems from the fact that when dealing with real or complex numbers, we can construct a sign function from < via Definition 7 and the order relation from the sign function via If we consider finite integral domains, however, suddenly it becomes less clear how to construct the < relation from the sign function, while the other way around still works by Definition 7. Given that we define circuits and logic fragments relative to an ordering, it is natural for both to have access to this ordering.Therefore, we choose to use < gates rather than sign gates.So in the following, all usages of sign are implicit uses of the order relation as by Definition 7.
In the cases which are considered in other literature (R or F 2 ), this has no complexity-theoretic impact, since in the emulation of one formalism using the other, we get a linear overhead in the size and constant overhead in the depth of the circuit.
In order to define complexity classes with respect to algebraic circuits, we have to define the function calculated by such a circuit and define the term of circuit families.
Definition 13.The (n ary) function f C : R n → R m computed by an R circuit C (with n input gates and m output gates) is defined by where y 1 , . . ., y m are the values of the output gates of C, when given x 1 , . . ., x n as its inputs.Definition 14.A family of R circuits C = (C n ) n∈N is a sequence of circuits which contains one circuit for every input length n ∈ N. The function f C : R * → R * computed by a circuit family C is defined by The size (resp.depth) of a circuit family (C n ) n∈N is defined as a function mapping n ∈ N to the size (resp.depth) of C n .
Analogously to the classical case, we say that a set S ⊆ R * can be decided by a circuit family C , if C can compute the characteristic function of S.
Definition 15.Let f 1 , f 2 : N → N be two functions.We then write UnbSizeDepth R (f 1 , f 2 ) to denote the class of sets decidable by R circuit families of size O(f 1 (n)) and depth O(f 2 (n)).We write SizeDepth R (f 1 , f 2 ) to denote the class of sets decidable by R circuit families of size O(f 1 (n)) and depth O(f 2 (n)), where each arithmetic gate has indegree bounded by 2 (we call this bounded fan-in).

Definition 16. AC
Remark 18.The circuit families we have just introduced do not have any restrictions on the difficulty of constructing any individual circuit given the input length.If it is important to know how hard obtaining a particular circuit is, one can consider so-called uniform circuit families.These families require their circuits to meet restrictions on the difficulties of obtaining them.For more information on uniformity, cf.(Vollmer, 1999).Uniformity criteria can be defined for algebraic circuit classes in a similar way.See for example (Blum et al., 1998, Section 18.5).

Structures and first-order logic over integral domains
As we want to characterize circuit complexity classes with logical fragments, this work falls broadly under the umbrella of finite model theory and, in particular, descriptive complexity.Foundational knowledge of these topics is assumed and can be found in the books by Grädel et al. (2007); Immerman (1999);and Libkin (2004).Traditionally, descriptive complexity is viewed as a subdiscipline of finite model theory.In our setting, however, we want to (carefully) introduce infinite structures to our reasoning.For this, we use metafinite model theory, an extension of the finite model formalism first introduced by (Grädel and Gurevich, 1998).A short introduction to metafinite model theory is also featured in the book by Grädel et al. 2007, page 210).The approach was taken by Grädel and Meer (1995) to describe some essential complexity classes over real numbers.These descriptions were later extended by Cucker and Meer (1999), where, among other things, the NC hierarchy over real numbers was defined.For their logical characterizations, these papers introduce a so-called first-order logic with arithmetics, which we will adapt to be used in our setting.
To make proofs easier, we will make use of the well-known trick that any predicate can be emulated by its characteristic function.Thus we only consider predicates, when convenient.We can furthermore emulate constants in the usual way by 0 ary functions.
Definition 19.Let L s , L f be finite vocabularies which only contain function symbols.An R structure of signature σ = (L s , L f ) is a pair D = (A , F) where 1.A is a finite structure of vocabulary L s which we call the skeleton of D whose universe A we will refer to as the universe of D and whose cardinality we will refer to by |A| 2. and F is a finite set which contains functions of the form X : A k → R for k ∈ N which interpret the function symbols in L f .
We will use STRUC R (σ ) to refer to the set of all R structures of signature σ , and we will assume that for any signature σ = (L s , L f ), the symbols in L s and L f are ordered.
Remark 20.In this paper, we only consider ranked structures, that is structures, in which the skeleton is ordered.
It often comes in handy to be able to encode an R structure D over a signature σ as an element of R * .We do so by simply concatenating the function values of all functions of D in lexicographical order with respect to the function arguments.
Definition 22 (First-order logic over R).The language of first-order logic over an integral domain R contains for each signature σ = (L s , L f ) a set of formulae and terms.The terms are divided into index terms which take values in universe of the skeleton and number terms which take values in R.These terms are inductively defined as follows: 1.The set of index terms is defined as the closure of the set of variables V under applications of the function symbols of L s .2. Any element of R is a number term.3.For index terms h 1 , . . ., h k and a k ary function symbol X ∈ L f , X(h 1 , . . ., h k ) is a number term. 4. If t 1 , t 2 are number terms, then so are t 1 + t 2 , t 1 × t 2 and sign(t 1 ).
Atomic formulae are equalities of index terms h 1 = h 2 and number terms t 1 = t 2 , inequalities of number terms t 1 < t 2 and expressions of the form P(h 1 , . . ., h k ), where P ∈ L s is a k-ary predicate symbol and h 1 , .., h k are index terms.
The set FO R is the smallest set which contains the closure of atomic formulae under the logical connectives {∧, ∨, ¬, →, ↔} and quantification ∃vψ and ∀vψ where v ranges over A .
For better readability, we will use inequalities of the form x ≤ y and the extensions of equalities x = y and the inequalities x < y and x ≤ y to tuples throughout this paper.Note that these extensions are easily definable from = and < in first-order logic.
Remark 23.We call any element of R a number term even though some integral domains can contain elements like ζ , ℵ or which are not numbers.
Equivalence of FO R formulae and sets defined by FO R formulae are done in the usual way, that is a formula ϕ defines a set S if and only if the elements of S are exactly the encodings of R structures under which ϕ holds and two such formulae are said to be equivalent if and only if they define the same set.
With the goal in mind to create a logic which can define sets decided by circuits with unbounded fan-in, we introduce new rules for building number terms: the sum and the product rule.We will also define a further rule, which we call the maximization rule.This one is, however, already definable in FO R , and we thus do not gain any expressive power by using it.We will use it to show that we can represent characteristic functions in FO R .
Definition 24 (Sum, product and maximization rule).Let t be a number term in which the variables x and the variables w occur freely and let A denote the universe of the given input structure.Then, is also a number term which is interpreted as x∈A |x| t(x, w).The number terms prod x (t(x, w)) and max x (t(x, w)) are defined analogously.
We call these operators aggregators, and for any formula ϕ containing aggregators of the above form, the variables in x are considered bound in ϕ.
Example 25.Let σ = ({}, {f 2 E }) be the signature of weighted graphs, that is L s is empty and L f contains the single function symbol f E which is interpreted such that f E (x, y) gives the weight of the edge from x to y or 0 if there is none.Let G be a (graph) structure over σ .Then, the following FO R + SUM R sentence ϕ states that there is a node in the skeleton of G , for which the sum of its outgoing edges is more than double the sum of the outgoing edges of any other node.
Proof.An occurrence of max i (F(i)) essentially assures that there exists an element x, such that for all elements y, F(x) ≥ F(y) and takes the value of F(x).Clearly, this can be defined in fist order logic by a formula of the form ∀x∃yF(x) ≥ F(y).
Furthermore, any characteristic function of a logical formula can be described in FO R .The proof for this runs analogously to that of Cucker and Meer 1999, Proposition 2), since this proof does not make any use of special properties of the reals.

AC
The proof idea is similar to the proof of the established result by Immerman which characterizes AC 0 via FO.
When using logics to check, whether a given R tuple would be accepted by a R circuit, one needs to think about how this R tuple would be interpreted as an R structure A .This can be done by interpreting it as the set of the circuit's input gates along with a single unary function f element : A → R mapping the ith input gate to the ith input of the circuit.We call this kind of structure a circuit structure.
In the following, we would like to extend FO R by additional functions and relations that are not given in the input structure.To that end, we make a small addition to Definition 19 where we defined R structures.Whenever we talk about R structures over a signature (L s , L f ), we now also consider structures over signatures of the form (L s , L f , L a ).The additional (also ordered) vocabulary L a does not have any effect on the R structure, but it contains function symbols, which can be used in a logical formula with this signature.This means that any R structure of signature (L s , L f ) is also an R structure of signature (L s , L f , L a ) for any vocabulary L a .The symbols in L a stand for functions that we will use to extend the expressive power of FO R to capture various complexity classes.
Definition 27.Let F be a set of finitary functions.We will write FO R [F] to denote the class of sets that can be defined by FO R sentences which can make use of the functions in F in addition to what they are given in their structure.
Formally, this means that FO R [F] describes exactly those sets S ⊆ R * for which there exists an FO R sentence ϕ over a signature σ = (L s , L f , L a ) such that for each length n, there is an interpretation I n interpreting the symbols in L a as elements of F such that for all R * tuples s of length n it holds that s ∈ S if and only if s encodes an R structure over (L s , L f , L a ) which models ϕ when using I n .
Example 28.Let us take as an example the scenario where we are given a graph as a structure but want to make use of additional functions to interpret that graph as a circuit, by having those functions determine the gate types of the nodes in the graph.We will use the signature σ = ({E 2 }, {}, {f 1 out , f 1 add , f 1 in }), and we will use a set of functions F = {F out,1 , F out,2 , . . ., F add,1 , F add,2 , . . ., F in,1 , F in,2 , . . .}, where each function is a characteristic function which maps the nodes of the graph to 1, if the gate type matches and 0, otherwise.Hence, if a node v is an addition gate, we have F add,1 (v) = 1 and F out,1 (v) = 0.The number in the subscript of the functions of F refers to the size of the encoding of the structure, for which the functions should be used.For example, F add,4 is used for structures that are encoded as elements of R 4 .Now suppose we are interested in those circuits where there exists an input gate that has an addition gate as a successor.A fitting FO R [F] sentence would be The reason why ϕ works is that for each n ∈ N, there exists an interpretation I n which maps the symbols used in ϕ to functions in F. This interpretation just maps f in to F in,n and f add to F add,n .
If we are now given a graph structure of a graph such as the first one in Figure 1, encoded as its adjacency matrix  which would amount to the R 16 tuple (0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0), then our interpretation I 16 would map f in to F in,16 and f add to F add,16 .This means that the set of encodings of circuits which have gate types according to F that contain at least one input gate followed by an addition gate sentence over σ such that for each n, the interpretation I n interprets the symbols f in and f add as elements of F, such that for all s ∈ R * it holds that s is an encoding of such a circuit if and only if the graph structure encoded by s satisfies ϕ.
Definition 29.We write Arb R to denote the set of all functions f : R k → R, where k ∈ N.
Theorem 30.Let R be an infinite integral domain.Then, Proof.The proof for this theorem works similarly to the construction for FO R and Vollmer, 2021), since this construction does not make use of any special properties of the real numbers.
The basic idea for this proof is that we first show that for any FO R [Arb R ] + SUM R + PROD R sentence ϕ, we can construct a circuit family which accepts its input if and only if the input encodes an R structure that satisfies ϕ.This is basically done by mimicking the behaviour of the logical operators of ϕ using the available gate types and evaluating the formula level by level.A universal quantifier as in ∀xϕ(x), for instance, is implemented by using a sign gate (obtained from < as per Definition 7) on top of a multiplication gate, which has the circuits for ϕ(a) for each a in the skeleton of the encoded structure as its predecessors.
To translate the semantics of FO R into a circuit, we can mostly use the same translations as in the proof for the real case, as for the most part only properties of integral domains are used.We need ring properties for most of these translations and in particular for universal quantifiers, we also need commutativity of multiplication and no zero dividers, hence we require integral domains.
We do need to change the translation for existential quantifiers and ∨, however.In the real case, the circuit for ∃xϕ(x) is constructed similarly to the universal case with a sign gate followed by an addition gate with the circuits for ϕ(a) for each a in the skeleton as its predecessors.Since there are infinite integral domains with characteristic greater than 0, that is where adding a positive amount of 1 elements can yield 0, this would not always produce the desired result.However, we can overcome this easily by translating ∃xϕ(x) to ¬∀x¬ϕ(x) and x ∨ y to ¬(¬x ∧ ¬y), as negation, universal quantifiers and ∧ are constructible with integral domain properties.
For the converse inclusion, a number term val d (g) is created which, when given a circuit family (C n ) n∈N , evaluates to the value of gate g if g is on the dth level of the respective circuit C n .For this purpose, functions encoding the structure of these circuits are given by the Arb R extension of the logic.These functions provide information about the gate type of each gate, their constant values if they are constant gates, their index if they are input gates and the edge relation of the circuit.
For this construction, with integral domain properties no changes need to be made to the formula in the real setting.

Algebraic Circuits and Guarded Functional Recursion
In this section, we generalize the logical characterizations of NC 1 and AC 1 by Durand et al. (2018) to the respective complexity classes over integral domains NC 1 R and AC 1 R .We furthermore extend this method to capture the entire NC R and AC R hierarchies.
In their paper, Durand, Haak and Vollmer use what they call guarded predicative recursion to extend first-order logic in order to capture the logarithmic depth circuit complexity classes NC 1 and AC 1 .This essentially amounts to a recursion operator, which halves a tuple of variables (in their numerical interpretation) which is handed down in each recursion step.This ensures that the total recursion depth is at most logarithmic.The halving of the variable tuple is performed by using the fact that addition is expressible in FO if BIT and < are expressible (Immerman, 1999) in the following way Note that we do not define the formula of the halving to be equality, since this is not possible for odd numbers.However, this is not an issue since we only want to bound the worst case recursion depth.In order to capture classes of polylogarithmic depth, we would like to find a suitable factor to replace 1 2 with, so that the recursion process has polylogarithmic depth as well.As it turns out, for any i ∈ N, we can assure a recursion depth of O(( log 2 n) i ) by using the factor 2 Observation 31.Any number n ∈ N can be multiplied by the factor 2 A more general version of this observation can be found in Lemma 58 in the appendix.Unfortunately, while it is simple to divide by 2 when the BIT predicate is available, it is not at all clear if multiplying by a factor such as 2 − log 2 n ( log 2 n) i can be done in first-order logic.We can, however, make use of the ability to divide by 2 in order to achieve polylogarithmic recursion depth, by instead of dividing a number, essentially dividing the digits of a base n number individually and carrying over once 0 is reached.Let us take for example the base 5 number 444.The previously mentioned process is illustrated in Table 1.The table is supposed to be read from top to bottom and then from left to right.
We divide the digits of 444 from the least to most the significant digit until 0 is reached.So, the first step is dividing the rightmost digit of 444 by 2, getting from 444 to 442.After two more divisions of that kind, we reach 0 and in the subsequent step we reset the rightmost digit and divide the second digit once.This works in a similar way to counting down, where instead of taking away 1 in each step, we divide by 2 and carry over in an analogous way.Notably, reaching 000 from 444 takes 63 = ( log 2 5 + 2) 3 − 1 steps.This is no coincidence: It can easily be shown that for any base n number of i digits, this sort of process reaches the smallest possible element after less than ( log 2 n − 1 + 2) i − 1 steps.
Since we wish to logically characterize languages decided by circuit families, it is useful to briefly talk about representation of numbers.In descriptive complexity, tuples of elements from a finite, ordered domain A are often associated with numbers.This is frequently done by interpreting the tuple as a base |A| number with each element of the tuple representing its position in the ordering of A.  Whenever we talk about the numerical interpretation of a tuple, we refer to this sort of interpretation.With this interpretation in mind, we now want to define a BIT predicate, which is needed to express divisions in our logic.In our definition, we assume that the most significant bit of j's binary representation is the bit at index 1: Definition 33.For any ranked structure with universe D, let the relation BIT 2 ⊆ D * × D * be defined as follows: BIT := {(i, j) | when i and j are taken as their numerical interpretations, the ith bit of the binary representation of j is 1, i, j ∈ D * } Note that the case D * = N yields the classical BIT predicate.With the BIT predicate and an order relation, we are now able to express division by 2 in first-order logic.We use the fact that whenever BIT and an order are available, we can express multiplication and addition of numerical interpretations of tuples (Immerman, 1999).This result was shown for plain first-order logic, and since our two-sorted first-order logic FO R is equivalent to first-order logic if the secondary component is ignored, we can apply it here as well.
We express division by 2 as follows: Note again that since the numerical interpretations of tuples are natural numbers, expressing x ≤ y/2 is really as good as we can do, since x = y/2 would not work for odd numbers.
Next, we will turn to defining the recursion operator which we have alluded to in the beginning of this section.First, we need a little bit of additional notation, that is relativized aggregators.
https://doi.org/10.1017/S0960129524000136Published online by Cambridge University Press A relativization of an aggregator is a formula restricting which elements are considered for the aggregator.
Notation 34.For a number term t and an FO R formula ϕ, we write as a shorthand for Analogously, we write and as a shorthand for In all these cases, we say that the term t(x) is in the scope of the respective aggregator.For example in the first case, t(x) is in the scope of the relativized aggregator max x .(ϕ(x)).
We now define the GFR i R operator and logics extended by GFR i R of the form L + GFR i R .The idea is to mimic the behaviour demonstrated in Table 1.
Definition 35 (GFR i R ).Let F be a set of functions such that BIT is definable in FO R [F] and let L be FO R [F] or a logic obtained by extending FO R [F] with some construction rules (such as the sum or the product rule as per Definition 24).
For i ≥ 0, the set of L + GFR i R formulae over σ = (L s , L f , L a ) is the set of formulae by the grammar for L over σ extended by the rule where ψ is an L formula, f is a function symbol, and t is an L number term with free variables x, y 1 , . . ., y i , y i+1 such that 1. all y j for 1 ≤ j ≤ i contain the same (positive) number of variables, 2. f only occurs in the form f (a, z 1 , . . ., z i , z i+1 ), where z 1 , . . ., z i , z i+1 are in the scope of a guarded aggregation with A ∈ {max, sum, prod}, ξ ∈ L and ξ not containing any symbols of L s or L f and 3. f never occurs in the scope of any aggregation (or quantification) not guarded in this way.

The function symbol f is considered bound in
The semantics for the GFR R i operator are defined as follows: Let ϕ be an L + GFR i R formula over σ with the single GFR i R occurrence [f (x, y 1 , . . ., y i , y i+1 ) ≡ t(x, y 1 , . . ., y i , y i+1 , f )]ψ(z, f ) and let D ∈ STRUC R (σ ).Then, the operator which is applied to the formula ψ, namely [f (x, y 1 , . . ., y i , y i+1 ) ≡ t(x, y 1 , . . ., y i , y i+1 , f )], defines the interpretation of f in ψ in the following way: For all tuples a, b 1 , . . ., b i , b i+1 of elements of the universe D of D with the same arities as x, y 1 , . . ., y i , y i+1 , respectively, This means that the formula [f (x, y 1 , . . ., y i , y i+1 ) ≡ t(x, y 1 , . . ., y i , y i+1 , f )]ψ(c, f ) holds for a tuple c ∈ D |c| with the same arity as z if and only if D |= ψ(c, f I ) where f I is the interpretation of f as defined by the GFR R i operator.Semantics of formulae with several GFR i R operators are defined analogously.
Note that the (i + 1)th tuple does not get restricted by the guarded aggregation.
An example is in order.In the following scenario, we would like to illustrate the use of the GFR i R operator.A more thorough examination of its recursion depth will follow in Lemma 37.
Example 36.Let us consider the scenario where we are given a graph G, two nodes s and t of G, and we wish to express that there is a path from s to t in G. Let the graphs we consider be encoded by a structure D, such that each node can be uniquely identified with a quadruple of values of the universe of D. The signature we will be using is σ ) encodes the target node and f E (x 1 , . . ., x 8 ) = 1 if there is an edge in G from the node encoded by (x 1 , x 2 , x 3 , x 4 ) to the node encoded by (x 5 , x 6 , x 7 , x 8 ).This means that, if D = (A , F), then the graph it encodes has size |A| 4 .
If we are interested in finding out whether there exists a path of length bounded by ( log n) 4 from the start node to the target node, we can use the following FO R + SUM R + PROD R + GFR 4 R sentence.(A more exact treatment of the recursion depth of the GFR i R operator will follow this example in Lemma 37.) In ϕ, we first identify the starting node and then dive into the recursion.Note first that the values y 5 , y 6 , y 7 , y 8 essentially take the place of the y i+1 in Definition 35.Note also that the values y 1 , y 2 , y 3 , y 4 take the place of the y 1 . . .y i in the aforementioned definition and are in this example essentially only used as a counter mimicking the behaviour shown in Table 1 to ensure the correct recursion depth.The point of m in ϕ is thus merely to essentially start this counter which will then become decreased in the recursion.We could also impose that m be the maximum value of the universe of D, but we do not need to, as if any such m exists, our requirement that a path with length bounded by O(( log n) 4 ) is satisfied.
In t, we first check whether we have already reached the target node.Afterwards, we use a guarded sum-aggregator to decrease the counter stored in z 1 , z 2 , z 3 , z 4 , iterate over all nodes z 5 , z 6 , z 7 , z 8 and jump into the recursion, zeroing out all non-neighbouring nodes of the current node.
In total, ϕ essentially describes an algorithm which traverses the given graph in a depth-first manner and which terminates after polylogarithmically many steps because of the guarded aggregations.The exact recursion depth is not obvious and will be investigated further in the following.
Having introduced the GFR i R operator, it remains to be shown that it indeed ensures polylogarithmic recursion depth in the way that we want it to.
Lemma 37. Let D ∈ STRUC R (σ ) and let ϕ be a formula containing a GFR i R operator.Then, the recursion depth of the GFR i R operator is bounded by O(( log 2 n) i ), where n is the size of the universe of D.
Proof.Let n be the size of the universe of the structure under which the GFR i R operator is interpreted.The bound for the recursion depth of the GFR i R operator stems from the relativization which guards the aggregated variables.Let f (x, z 1 , . . ., z i , z i+1 ) be an occurrence of a GPR i operator.Then, the variables in z 1 , . . ., z i , z i+1 are in the scope of a guarded aggregation of the form Let z j be the numerical interpretation of z j for all 1 ≤ j ≤ i.We interpret the tuple z 1 , . . ., z i as a natural number z of base n where the jth digit of z is z j .
First, observe that in this interpretation, the relativization of the variables used in the recursive call ensures that z strictly decreases in each step.The big disjunction makes sure that there is an index j, such that z j ≤ y j /2, which means that the numerical interpretation of z j is at most half of the numerical interpretation of y j .It also ensures that all tuples with smaller indices z k (i.e., the more significant tuples in the interpretation of z 1 , . . ., z i as a base n number) do not increase.
Since each of the tuples z j (in their numerical interpretation) can only get halved at most log 2 n + 1 times before reaching 0, it takes at most log 2 n + 2 recursion steps until a tuple other than the ith has been halved, in the worst case that is the (i − 1)th tuple.This process can then be repeated at most log 2 n + 1 times, before the tuple at the next lower index gets halved.In total, in the worst case, it takes ( log 2 n + 2) j recursion steps until the i − jth tuple gets halved in this process.
This means that after ( log 2 n + 2) i − 1 recursion steps, each tuple has reached 0. Therefore, the total maximum recursion depth is ( log This process can be thought of as counting down a base log 2 n number.The idea for it has already been visualized in Table 1.It is also explicitly illustrated in Tables 3 and 4 in the appendix, for a sequence which we will define shortly in Definition 42 to make use of exactly this kind of process.
Since our final goal is to characterize both AC i R and NC i R , we need to also define aggregators which model the properties of NC R circuits.For this purpose, we introduce bounded aggregators, that is relativized aggregators where we only consider the two elements of maximal size meeting the condition in the relativization.
Definition 38.We define the bounded aggregators sum x,bound and prod x,bound .They are used in the same way as the aggregators defined earlier in Definition 24.The semantics are defined as follows: The bounded aggregators prod x,bound and max x,bound are defined analogously.
With this bounded aggregation, we can now define a slightly weaker version of the guarded functional recursion from Definition 35, which we call bounded guarded functional recursion GFR i R,bound .This allows us then to define logics of the form FO R Definition 39 bound if the same conditions as in Definition 35 are met, but instead of a guarded aggregation in (2), we require a bounded guarded aggregation.
Our goal in the following is to characterize the AC R and NC R hierarchies using first-order logic and guarded functional recursion.For that purpose, we now define a sequence which we will later use as part of the numbers of our gates in order to encode the gates' depth into their numbers.The idea behind the construction of this sequence will be that for a circuit family (C n ) n∈N with depth bounded by c • ( log 2 n) i , each of the sequence's elements is essentially a i digit base c • log 2 n − 1 number with each digit being encoded in unary and padded by zeroes.For readability purposes, we will refer to this encoding simply as a unary encoding.The sequence can then be seen as counting down to 0 in that interpretation.This will then result in a length of c i • log 2 n i ∈ O(( log 2 n) i ) for fixed i.We begin by introducing our conventions regarding unary encodings of numbers.We now proceed to define the aforementioned sequence d which we will later use to essentially encode our circuits' gates' depth into their gate numbers.Definition 42.For each n, c, i ∈ N >0 , we define the sequence d(n, c, i) as follows.For readability purposes, we leave out the arguments (n, c, i) in the definition of the sequence and only write d instead of d(n, c, i).

Each element d of d consists of i tuples d
otherwise, for all where d = 0 . . .0.

d
Table 2 shows an abbreviated example for the sequence d.A further example as well as the full version of Table 2 can be found in the appendix as Tables 3 and 4.
Remark 43.Note that substracting the value 1 in this unary encoding can be seen as an integer division by 2 in binary.This will become useful later when putting this into the context of guarded functional recursion with BIT.Note that the length (i.e. the number of elements) of d(8, 1, 2) is This is no coincidence.Next, we show that this observation holds in general.
Lemma 44.Let n, c, i ∈ N >0 .Then, d(n, c, i) has length c i • log 2 n i .
Proof.Since for each element e in d (n, c, i) the successor rule can be interpreted as subtracting 1 from e when e is seen as a base c • log 2 n number with i digits, we are starting at the largest possible element in that sense (i.e. 1 . . . 1, which would correspond to (c • log 2 n ) i − 1) and we are counting down to the lowest possible element (i.e. 0 . . .0, corresponding to 0), there are exactly (c The remaining problem that stands in the way of using the sequence d for the numbering of gates in descriptions for circuits is that the length of the elements in d depends on n (which will be the number of input gates of our circuit).However, we can remedy this, since we essentially have access to base n numbers in the description for a circuit with n input gates (by virtue of interpreting circuit inputs as circuit structures).Combining those with the BIT predicate and now interpreting the unary encoded tuples in elements of d as binary numbers allows us to encode elements of d using a constant number of digits.We can thus encode the binary valuations of tuples in elements of d as base n numbers of length c.Therefore, each element of d can be encoded using i base n numbers of length c (or i • c base n digits).
Before we proceed to use the sequence d for circuit descriptions, we need one more lemma which provides a useful property of AC i R resp.NC i R circuits.We would like to be able to talk about the depth of gates, that is the distance of a gate to the input gates of the circuit.For this reason, we will establish the fact that for the circuit families we investigate, circuits exist where for each gate g, each input g path has the same length.

Lemma 46. Let L be in AC
Then, there exists a circuit family C = (C n ) n∈N deciding L, such that for all n ∈ N and each gate g in C n , each path from an input gate to g in C n has the same length.We call C n a balanced DAG.
The lemma follows from standard circuit manipulation (cf.also (Vollmer, 1999, Exercise 4.35)).For convenience, a proof is provided in the appendix.
As previously mentioned, whenever we are dealing with balanced DAGs, we will refer to the unambiguous length from input gates to a gate g as the depth of g.Now we will turn to a lemma which will then finally enable us to use the previously defined sequence d to encode our gates' depth into their circuit numbers.The idea is for a gate g, to prepend the depth(g)th element of d to the gate number of g.This way each path from an input gate to the output essentially contains elements of d in order in the prefixes of its gate numbers.This, combined with Lemma 44, provides us with a way to logically ensure the polylogarithmic depth of a circuit given as a circuit structure.

Lemma 47. Let L be in AC
Then, there exists an AC i R (resp.NC i R ) circuit family C = (C n ) n∈N deciding L with depth bounded by c • ( log 2 n) i , such that each circuit in C is a balanced DAG, numbered by base n numbers and each gate g in C encodes the depth(g)'s element of d in the first c • i digits of its gate number.
The numbering after the first c • i digits can be chosen arbitrarily.
Without loss of generality, let the circuits of C be balanced DAGs as per Lemma 46.That means that for each circuit C n in C , for each gate g in C n , the length of all paths from input gates to g is the same.Let c ∈ N >0 be such that c i • log 2 n i is larger than the depth of C n (which is bounded by c 1 • ( log 2 n) i ).We pad each path in C n to length c i • log 2 n i by replacing each edge from an input gate to a gate in C n by a path of dummy gates of length c i • log 2 n i − depth(C n ) so that the resulting circuit has exactly depth c i • log 2 n i .
We now use any base n numbering for the gates of C n and for each gate g prepend the depth(g)th element of d (n, c, i) to the number of g.Since we made sure that each input-outputpath in C n has length exactly c i • log 2 n i , we can encode exactly the sequence d (n, c, i) in the numbers of each input-output-path.So now for each input-output-path, the first c • i digits of gate numbers encode the elements of d (n, c, i) in the order that they appear in the sequence.
With the normal form from Lemma 47 and the previous definitions, we can now turn to a theorem characterizing AC i R and NC i R logically by tying it all together.

AC
Proof.We start by showing the inclusions of the circuit classes in the respective logics and will then proceed with the converse directions.
Step 1: As the circuit input is interpreted as a circuit structure, the signature σ of ϕ contains only the single unary function symbol f element .
We define the following additional relations and functions which will essentially encode our given circuits.We will have access to them because of the Arb R extension of our logic and we use relations here instead of functions for ease of reading, since we essentially have access to relations in functional structures if we consider the respective characteristic functions of the relations instead.
• G × (x) ⇐⇒ x is a multiplication gate.• G < (x) ⇐⇒ x is a < gate, the left predecessor of which is lexicographically lower than the right predecessor.
x is a constant gate and y = 0 otherwise.Without loss of generality let all circuits of C be in the normal form of Lemma 47 and let the numbering of C n be such that the last digit of the number of the jth input gate is j for 1 ≤ j ≤ n.Recall that this means that for each gate number of a gate g represented as a tuple g, the first c • i elements of g encode the depth(g)th element of d (n, c, i).The following sentence ϕ defines L: where t is defined as follows (with z j denoting the jth c long subtuple in the c • i long prefix of z, which, as per the normal form of Lemma 47, encodes the jth tuple of an element of d(n, c, i)): Here, the relations G g (y) for g ∈ {+, ×, <, input, const, output} give information about the gate type of the gate encoded by y and are provided by the Arb R extension of FO R .They are interpreted as mentioned above.The BIT predicate is provided in the same way.
We will now prove that ϕ does indeed define L. Let a ∈ R n be the input to C n .We will show that for all g ∈ R l , where l is the encoding length of a gate in C , the value of the gate encoded by g in the computation of C n when C n is given a as the input is f (g).Let g be the gate encoded by g.We will argue by induction on the depth of the gate g, that is by the distance between g and an input gate.d = 0: If d = 0, then g is an input gate.Therefore, the only summand in t(g, f ) that is not trivially 0 is the fourth one, which is equal to f element (g |g| ) (which is the value of the g |g| th input gate).
d → d + 1: Since d + 1 > 0, g is not an input gate.This means that there are the following 5 possibilities for g: 1. g is an addition gate: In that case, the only summand in t(g, f ) which is not trivially 0 is the first one.All predecessors of g have a number, the first c • i digits of which are the successor of the first c • i digits of g in the sequence d(n, c, i) because of the normal form of Lemma 47.Additionally, the relativization ensures that the gate encoded by z in the respective summand has exactly the successor in the sequence d(n, c, i) of g's first c • i digits in its first c • i digits.This means that by the induction hypothesis yields exactly the sum of all the values of predecessor gates of g. 2. g is a multiplication gate: Analogously to the above case, yields exactly the product of all predecessor gates of g. 3. g is a < gate: In that case, the relativization makes sure that z is the maximum gate number of a predecessor of g and makes sure that b is the gate number of the other predecessor of g and that therefore χ[f (b) < f (z)] is the value of t(g, f ), which is exactly the value of g in the computation of C n .4. g is a constant gate: Since f const_val (g) returns exactly the constant that g is labelled with, that value is taken by g. 5. g is the output gate: In that case, g only has one predecessor and thus ensures that g takes the value of that predecessor, since there is only one element matching the relativization.

Finally, by
we make sure that there exists an output gate which has the value 1 at the end of the computation.
Step 2: The proof for this inclusion follows in the same way as the proof for the AC i R case, by just replacing all guarded aggregations in the formulae by bounded guarded aggregations. Step R via a formula ϕ over some signature σ = (L s , L f , L a ) and let there be only one occurrence of a GFR i R operator in ϕ.This proof easily extends to the general case.This means that ϕ is of the form We first construct an AC i R family evaluating ϕ without the occurrences of f as in Theorem 30.This is possible, since ϕ is an FO R [Arb R ] + SUM R + PROD R formula over (L s , L f , L a ∪ {f }), and by Theorem 30, there is such a circuit family for ϕ.
Next, we explain how we build an AC i R circuit family for the whole formula ϕ from this point.For this, we need to construct an AC i R circuit family computing the value of f (x, y) for each pair a, b with a ∈ A |x| for some k ∈ N and b i number term and can therefore be evaluated by an AC 0 R circuit family, except for the occurrences of f .We now obtain C n by taking the nth circuit of all those (polynomially many) AC 0 R circuit families and for all a, b replacing the gate labelled f (a, b) by the output gate of the circuit computing t(a, b, f ).
Since all occurrences of f (x, y) are in the scope of a guarded aggregation R circuit and therefore has constant depth, in total, any path from the first recursive call to the termination has length in O(( log 2 n) i ).Since the starting circuit deciding ϕ had constant depth, the circuit we constructed now has polylogarithmic depth in total.And given that we only added polynomially many subcircuits with polynomially many gates each, the whole circuit is an AC i R circuit deciding ϕ.For the general case of several GFR i R operators, we construct a circuit for each operator in the same way and connect them to the circuit evaluating ϕ. Step This case can be proven analogously to the case for AC i R .Instead of AC 0 R families for evaluating ϕ and t, we now need to use NC 1 R families, which is why this result only holds for i > 0. With this, we have logarithmic depth for evaluating t, which would generally be a problem, since repeating this ( log 2 n) i times would yield a NC i+1 R family.However, this would only be the case, if the f gate (which would later be replaced by an edge to another copy of the circuit evaluating t) was to occur at logarithmic depth in the circuit evaluating t.Fortunately, due to our requirement that f must never occur in the scope of any unbounded quantifier or aggregator, this is not the case, because the only cases where unbounded fan-in gates would be needed are the ones of unbounded quantifiers and aggregators.
It remains to be shown that evaluating a number term without unbounded quantifiers and aggregators can be done in constant depth with bounded fan-in, that is in NC 0 R .This might seem surprising at first glance, as NC 0 R circuits can essentially only access a constant number of their input gates.However, if no unbounded quantifiers or aggregators are present, FO R [Arb R ] + SUM R + PROD R number terms only contain variables introduced by bounded aggregators or quantifiers, and their behaviour can essentially be hardwired.We will now show that the bounded aggregators do not introduce logarithmic depth, because, as mentioned above, only the unbounded quantifiers and aggregators would require unbounded fan-in gates and thus introduce logarithmic depth when being restricted to bounded fan-in.The saving grace here is that we only need to aggregate over the maximum two elements which satisfy the relativization of the bounded aggregation.The relativization only depends on the ranking of the input structure and not on the actual functions and relations given therein.Since the ranking is implicitly given to the circuit by the length of the input structure's encoding and thus the number of input gates of the circuit, we thus essentially hard-code, which the two maximum elements satisfying the relativization are.Once we have done that we can simply use a single addition (multiplication) gate to mimic the behaviour of a bounded sum (product) construction which has as its two predecessors the circuits for the term, which is being aggregated over, with the two aforementioned maximum values satisfying the relativization.
Putting this all together, f gates only ever occur at constant depth in the circuit for t, and thus, replacing this gate by a copy of the circuit for t and doing this iteratively ( log n) i many times yields a circuit of depth O(( log n) i ).
As mentioned previously, the basis of the idea for guarded functional recursion was the guarded predicative recursion used for plain first-order logic (Durand et al., 2018).The same extension to polylogarithmic recursion depth that was showcased in this paper for GFR R can be applied to GPR.Similarly to the relativized aggregators in Notation 34, for relativized quantifiers, we write (∃x 1 , . . ., x k .ϕ)ψas a shorthand for ∃x 1 . . .∃x k (ϕ ∧ ψ) and (∀x 1 , . . ., x k .ϕ)ψas a shorthand for ∀x 1 , . . ., x k (ϕ → ψ).
For an FO formula ϕ and a relation variable P, we write ϕ(P + ) if P does not occur in the scope of a negation in ϕ.
with ξ not containing any relation symbols for relations given in the input structure and 2. never occurs in the scope of any quantification not guarded this way.
The semantics for GPR i are defined analogously to the semantics for GFR i R in Definition 35.
As stated, the proof of Theorem 48 can easily be adapted to the GPR i operator, so we obtain the following result.
Corollary 50.circuit by an AC 0 Z 2 circuit by simulating the operations defined in the integral domain Z 3 by operations of tuples of Z 2 .To formalize this intuition, we propose the notion of C simulation maps.Since the focus of this paper is on circuit complexity, we introduce simulation maps only in the context of circuit size and depth, but this formalism does not depend on specific properties of circuits and can easily be adapted to time and space complexity classes, which can, for example be defined via a suitably adapted definition of R machines as presented in (Blum et al., 1998).

FO[Arb]
A C simulation map from an integral domain R 1 to an integral domain R 2 is an injective function f : R * 1 → R * 2 such that the following holds: For all k ∈ N >0 and A ∈ C R k 1 , there exists an ∈ N >0 and a language B ∈ C R 2 such that for all If there exists a C simulation map from an integral domain R 1 to an integral domain R 2 , we also write C R 1 ⊆ sim C R 2 .The relations = sim and sim are defined analogously.
Similar to the formalism of reductions in classical complexity theory, the relation induced by ⊆ sim C is reflexive and transitive.Since in this work the main focus is on the AC R and NC R hierarchies, we will proceed to restrict ourselves to these classes.But note that the simulation methods we show trivially extend to larger complexity classes.
The formalism essentially divides our integral domains into a three-tier hierarchy.The first tier in this hierarchy consists of the complexity classes over finite integral domains, the second tier consists of the classes over integral domains which are simulatable by Z, and the third tier consists of classes over integral domains which are simulatable by R. In this setting, a complexity class over a certain integral domain is able to simulate the complexity classes over integral domains in the same tier or below.To make this explicit, we show the following three equalities: Theorem 52.The following three equations hold: 1. NC i F p = sim NC i F q for all prime powers p, q and i ∈ N.

NC
Proof.We split the proof into two main parts: the finite case, in which simulations of integral domains are trivial, and the infinite case, where we have to be more careful about the new operations our simulating circuits execute to uphold that the structure of the circuits simulate are still integral domains.
The finite case.The simulation of finite integral domains is quite trivial.For NC i F p ⊆ sim NC i F q where p ≤ q, the simulation is straightforward.For NC i F p ⊆ sim NC i F q where p > q, choose the length of tuples that the NC i F q circuit uses to be the smallest k ∈ N such that p ≤ q k holds.Map the p elements to the first p elements in F k q and define addition and multiplication tables of constant size which simulate the addition and multiplication in F p .
The infinite case.We will prove that NC i Z = sim NC i Z[j k ] for any fixed k ∈ N. Note that the following proof does not depend on the countability of the set, so the proof for the uncountable case runs analogously.The direction NC i Z ⊆ sim NC i Z[j k ] is trivial.In the other direction, note that when simulating infinite integral domains, we can no longer hard-code the addition and multiplication tables in a trivial way.Furthermore, integral domains are not closed under cartesian products, since for two integral domains R 1 , R 2 , we have for R 1 × R 2 that (1, 0) × (0, 1) = (0, 0) using componentwise multiplication.We fix this by still using k tuples to emulate the adjoint elements and using componentwise addition, but adapting multiplication so that it simulates multiplication of two elements with adjoint elements, where the mth index of the tuple stands for the mth power of the adjoint element, which we call j here.Explicitly, we use the integral domain (Z k , + Z k , × Z k ), where + Z k is componentwise addition, and × Z k is defined as follows: If we want to multiply two tuples of length k we simulate the multiplication in the original, adjoint integral domain by constructing the following matrix of constant size which corresponds to expanding the multiplication: Observe that, due to the fact that j k = −1, every entry a uv of the matrix contributes to the term at index (u + v − 2) mod k in the tuple.The entry of the resulting tuple z at index is thus Theorem 53.The following three equations hold: 1. AC i F p = sim AC i F q for all prime powers p, q and i ∈ N.

AC
Proof.We use the strategy from the proof of Theorem 52 and show that unbounded addition and multiplication can be realized without a significant increase in the complexity.
For n given tuples of length k (x 1,1 , x 1,2 , . . ., x 1,k ), (x 2,1 , x 2,2 , . . ., x 2,k ), . . ., (x n,1 , x n,2 , . . ., x n,k ), the simulation of unbounded addition by unbounded componentwise addition of tuples is straightforward.For unbounded multiplication, we extend the strategy for the bounded case by computing the matrix A iteratively.That is, for a sequence of tuples x 1 , . . ., x n , first compute the matrix A 1 from the tuples x 1 and x 2 , resulting in a tuple z 1 .The matrix A 2 is then computed from the tuples z 1 and x 3 , and so on.In the resulting tuple z, the value of each tuple entry can only depend on the values x i,j .So to simulate an unbounded multiplication gate, we need only an unbounded multiplication gate with a linear number of predecessors.
Corollary 54.For all i ∈ N, we have Lemma 55.For all i ∈ N, we have Proof.We use the fact that R is a transcendental field extension of Q, that is there is no finite set of numbers M which we can adjoin to Q in order to get Q[M] = R.In our setting, this means that we cannot simulate all numbers r ∈ R by a set of finite tuples (a 0 , . . ., a n ) of numbers where a 0 , . . ., a n ∈ Q.

Conclusion
In this paper, we introduced algebraic complexity classes with respect to algebraic circuits over integral domains.We showed a logical characterization for AC 0 R and further characterizations for the AC R and NC R hierarchies, using a generalization of the GPR operator of Durand et al. (2018).We constructed a formalism to be able to compare the expressiveness of complexity classes with different underlying integral domains.We then showed that using this formalism, we obtain a hierarchy of sets of complexity classes, each set being able to "simulate" the complexity classes from the sets below.
For future work, it would be interesting to investigate the logical characterizations made in this paper in the uniform setting.We know that for the real numbers, the characterization AC 0 R = FO R [Arb R ] + SUM R + PROD R holds both non-uniformly and for uniformity criteria given by polynomial time computable circuits (P R uniform), logarithmic time computable circuits (LT R uniform) and first-order definable circuits (FO R uniform) (Barlag and Vollmer, 2021).We believe that the results we presented here hold in analogous uniform settings as well, though this would need to be further examined.The case of P R uniformity seems like it should follow relatively directly with similar ideas as in the AC 0 R setting.For LT R and FO R uniformity, though, some more work would be required, since polylogarithmic depth can neither be trivially simulated in logarithmic time nor can it be simply encoded in fixed length gate numbers, which is how the proofs for the real cases go.However, the periodic nature of the circuits simulating GFR i R extensions makes it plausible, and they are describable in a more compact way.
Another open direction is to find interesting problems (potentially even complete) for these new complexity classes.This could even provide new insights for the classical case.
A promising approach to the separation of algebraic circuit complexity classes could be an adaption of the approach taken by Cucker, who showed that the problem FER, which essentially asks whether a point lies on a Fermat curve, separates the (logarithmic time uniform) NC i R classes (Cucker, 1992).The same proof could also hold for the NC i C classes.
Another model deserving of the name "algebraic circuit" is arithmetic circuits in the sense of Valiant (1979).This model is similar to the model presented here, with the exception that generally, only addition and multiplication gates are permitted.Hence, there is no sign or comparison function, which gives easy access to control flow constructions such as conditional statements and also allows for the study of functions which are not differentiable.Maybe the ideas presented in this paper can lead to further insights with regard to this model of computation as well.
In the Boolean case, in addition to the AC and NC hierarchies, one commonly investigated hierarchy is the so-called SAC hierarchy.This hierarchy is defined by bounding the fan-in of only one gate type, that is either the conjunction or the disjunction gates.It is known that it does not make a difference in that setting which gate type is bounded.A possible next step is to define a sensible analogue of the SAC hierarchy in the algebraic setting or as a previous step in the real setting.We believe that in the algebraic case, it does make a difference which gate type we bound.The next step is to decide which version of bounded gates yields the more interesting class and afterwards one can relate it to any GPR i like operator in the real or the algebraic setting.This model could then possibly be useful to investigate algebraic structures where the respective operations do not adhere to the same axioms.Proof.We want to bound the depth of the circuit (i.e., the number of layers k) by the sublinear function f .For any input size n, we therefore set k = f (n) < n.Furthermore, if we require that the inequality g C (k) ≤ α • g C (k − 1) holds, the circuit reaches its maximum depth when nα k ≤ 1 holds, since the factor of α is applied k times, once for each layer.Substitution yields Corollary 59.A circuit C has depth O(( log 2 n) i ) if we request that for every layer k, the inequality g C (k) ≤ 2  3 shows the sequence d(8, 1, 2).Since c • log 2 8 − 1 = 2, each element of d(8, 1, 2) contains i = 2 tuples of length 2. Each line is one element of the sequence, and the columns determine the tuples in the elements.This means that the first element here is the element (11,11), the second one is (11, 01) and so on.
Table 4 shows the sequence d(8, 2, 2).Since c • log 2 8 − 1 = 5, each element of d(8, 2, 2) contains i = 2 tuples of length 5.Each line is one element of the sequence, and the columns determine the tuples in the elements.This means that the first element here is the element (11111,11111), the second one is (11111, 01111) and so on.

Figure 1 .
Figure 1.Example graphs that satisfy the imposed conditions of Example 28.

Example 32 .
For example, let D = {a, b, c, d} be ordered such that a < b < c < d.Then, the tuple (b, d, c, a) = (1, 3, 2, 0) would be interpreted as the base 4 number 1320, which would correspond to 60 in decimal.

Definition 40 .
Let n, ∈ N such that ≥ n.Then, we will refer to the function unary : N → {0, 1} defined as unary (n) := 0 −n 1 n as the (length ) unary encoding of n.Definition 41.For any binary string a of the form a = 0 k−m 1 m for some k, m, we define the function uval : {0, 1} → N defined as uval(a) := m and call uval(a) the value of the unary encoding a.

Observation 45 .
Let n, c ∈ N >0 and 1 ≤ ≤ c • log 2 n .The number 2 − 1 can be encoded by a base n number of length c.Proof.The largest possible number of that form is 2 c• log 2 n − 1 ≤ n c − 1, which corresponds to "n − 1 . . .n − 1 c times " in base n.Therefore, 2 c• log 2 n − 1 can be encoded with c base n digits and thus also all smaller natural numbers can be encoded in this way.
the number of steps from any f (a, b) before reaching a function call of the form f (c, 0, d), with |c| = |x| and |d| = |y i+1 |, terminating the recursion, is bounded by O(( log 2 n) i ) as per Lemma 37. Since each such step -computing f (a 1 , b 1 ), when given values of the next recursive call f (a 2 , b 2 ) -is done by an AC 0

Definition 57 .
Let C be a circuit and let L k be the set of all gates g ∈ C with depth(g) = k.Then, we call L k the kth layer of C. Lemma 58.Let C = (C n ) n∈N be a circuit family, f a sublinear function and g C (k) the number of gates at layer k for a circuit C ∈ C .Furthermore, let α := 2 − log 2 n f (n) .A circuit C has depth O(f (n)) if we request that for every layer k, the inequality g C (k) ≤ α • g C (k − 1) holds.
n) i • g C (k − 1) holds.B. Examples for the Sequence d(n, c, i)Here, we develop two examples of the sequence d(n, c, i) from Definition 42.Table doi.org/10.1017/S0960129524000136Published online by Cambridge University Press

Relationship Between Versions of AC 0 R Over Different Integral Domains
org/10.1017/S0960129524000136Published online by Cambridge University Press5.Intuitively, a circuit deciding a problem in AC 0R should also be able to simulate circuits deciding problems in, for example, AC 0 Z and AC 0 Z 2 .Furthermore, we should be able to simulate an AC 0