Frequency analysis of load modulation networks for asymmetric Doherty power amplifiers in GaN

Abstract This paper investigates the frequency response of load modulation networks for asymmetric Doherty power amplifiers (ADPA) with an output back-off power level larger than 6 dB and a power ratio of peak to main amplifier (N − 1) larger than 1. The influence of the main path impedance transformer (IT) on the Doherty impedances at main and peak path as well as on the ADPA's efficiency is analyzed. Scaling of the main IT's characteristic impedance via ξ indicates a maximum broadband matching for an input voltage Vin of ξ · Vin,max. By weighting the frequency- and ξ-dependent efficiency curves using a probability density function (PDF), an optimum is obtained for ξ = 1/N. To verify the theory, three ADPAs with different ξ-scaled ITs are designed, measured, and compared. For the design at 3.6 GHz, a gallium nitride (GaN) transistor is used. By means of the intrinsic node matching technique, matching at the current source plane is obtained. In laboratory measurements, the ADPA with ξ = 1/N achieves a power-added efficiency (PAE) of 63% at 42 dBm output power and a PDF-weighted average PAE of 38.8% within 400 MHz bandwidth for 8 dB peak-to-average power ratio. Comparison with similar state-of-the-art ADPAs in GaN technology shows highest PAE and operation power gain GP for center frequencies larger than 3.0 GHz.


Introduction
The design of next generation wireless communication systems revolves around two main aspects: increasing data rates and power efficiency. In order to meet these growing demands, modulation schemes with instantaneous bandwidths of more than 200 MHz and dynamic ranges with peak-to-average-ratios (PAPR) of up to 12 dB are utilized to ensure gigabit-per-second transmission in the sub 6 Ghz frequency bands.
In a radio frequency transmitter, the major part of power consumption is caused by the power amplifier (PA). Hence, an energy-efficient system has to tap into its maximum power saving potential. Since an analog amplifier reaches maximum drain efficiency (DE) merely at maximum output power, several topologies, such as envelope tracking, out-phasing, or Doherty PA (DPA) [1], have been proposed to increase efficiency in the output back-off (OBO) region. The DPA topology will be the focal point of this work with an in-depth examination of its broadband behavior. This paper builds upon previous works [2,3] which identify the impedance transformer (IT) as bandwidth bottleneck by analyzing the frequency response of the Doherty load modulation network. Furthermore, the ITs' impact on the Doherty impedances at the main path Z M and peak path Z P is demonstrated in [4]. A comprehensive overview of investigated techniques for bandwidth extension (e.g. modification of the output network, parasitic compensation, dual-input, and transformer-less load modulation) is provided in [5]. However, these investigations are always based on the symmetric DPA topology with OBO = 6 dB, neglecting signals with a PAPR above 6 dB.
In this work, previous frequency analyses are extended by including the asymmetric DPA (ADPA) with an OBO larger than 6 dB. Further, the effects of the main path IT on the DE, Z M , and Z P for broadband performance are examined.
A scaling factor ξ, which is used to vary the characteristic impedance of the main path IT, is introduced in the theory section "Analysis of the asymmetric Doherty modulation network with a scaled impedance transformer". Depending on ξ, a maximum broadband matching of the main amplifier at a specific input level can be achieved. By weighting the frequencyand ξ-dependent efficiency curves using Rayleigh distributed probability density function (PDF), an optimum is found at ξ = 1/N. This theory is proven by the design of three amplifiers with different values of ξ. The design procedure at 3.6 GHz is described in section "Design process of the proposed Doherty power amplifier". For the design, a commercial gallium nitride (GaN) transistor model, which enables an intrinsic node matching technique, is used. The results obtained from laboratory measurements are presented in section "Experimental results" and finally compared with the state-ofthe-art in section "Conclusion". Leading up to the theoretical analyses in section "Analysis of the asymmetric Doherty modulation network with a scaled impedance transformer", the introduction section contains a brief review of the classical Doherty architecture.
Underlined parameters in this work, such as α t or Z M , indicate a complex value.

Classical Doherty load modulation network
A classical symmetric Doherty modulation network is shown in Fig. 1. At the common node of the main and peak path an impedance Z com = Z 0 /2 is provided. Moreover, Z 0 determines the impedances Z M and Z P . Those impedances further depend on the modulation index after impedance transformation α t , which is the ratio of the peak path current I P to the transformed main path current I M,t . Since the peak amplifier must provide the same output current as the main amplifier at maximum input voltage V in,max and no current below the back-off threshold at V in,max /2, α t is described by Thus, a voltage amplitude at the peak amplifier input V in,P occurs for V in > V in,max /2. This is realized by class C biasing of the peak amplifier.
Impedances provided by the classical Doherty modulation network Z M and Z P are now determined at the output node of the voltagecontrolled current sources. The transformed impedance Z M,t after the IT of the main path TL 0 is calculated with and transformed by TL 0 to .
The Doherty impedance of the peak path Z P is determined with To transform the load impedance R L to Z com , a second λ/4 IT TL 1 with the characteristic impedance is used.
Analysis of the asymmetric Doherty modulation network with a scaled impedance transformer As described in a previous work [6], it is advantageous to modify the classical (symmetric) Doherty modulation network toward an asymmetric Doherty modulation network. This enables a more efficient performance for signals with a PAPR > 6 dB. The output power ratio between peak amplifier P out,P and main amplifier P out,M can be described by For an asymmetric topology with OBO larger than 6 dB, (N − 1) is larger than 1. The load modulation in dependence of N was thoroughly investigated in [6], however a frequency analyses was not carried out and shall be part of the proposed work.
Determination of the impedance Z 0 The common node impedance Z com in an asymmetric Doherty modulation network is Z 0 /N. As depicted in Fig. 2 it is transformed from the load R L by TL 1 with a characteristic impedance Z 1 of For a classical DPA, the frequency response of Z com is analyzed in [5]. In case of a more general asymmetric topology, this expands to For m = 1, the frequency dependent part of (8) is canceled. This is achieved at By inserting (10) into (8) one obtains thus no bandwidth limiting IT is necessary and TL 1 can be omitted. If for design reasons a Z 0 different from (10) is necessary, a broadband post matching network should be used. Several works, such as [4,7], provide solutions for this task.

Main path impedance provided by a Doherty modulation network with scaled impedance transformer
The characteristic impedance of TL 0 can be chosen freely, even if Z 0 is already defined by (10). Hence, ξ is now introduced as scaling variable. For the proposed Doherty load modulation network in Fig. 2, the impedance analysis is carried out at the output nodes of the ideal current sources as reference plane. According to (3), the extended calculation for Z M follows: .
The ratio of the peak path to the main path current needs to satisfy the equation to ensure the correct ratio of I M,t and I P at the common node for V in = V in,max .

Frequency analysis of the load modulation in the main path
The previous calculations are only valid at the design frequency f 0 . However, the topology related λ/4 IT TL 0 lowers the ADPA's bandwidth independently of the main or peak amplifier bandwidth. Z M and Z P are real-valued at f 0 . Below and above this frequency, imaginary parts occur and subsequently the real part changes. This causes mismatch and thus a reduction in the efficiency of the amplifier. Moreover, a phase shift between the main and peak path current appears at the common node of the main and peak path, which is not compensated by the λ/4 IT at the peak amplifier input. The summation of I M,t and I P becomes complex-valued, thus the ratio α t , previously defined in (1), also depends on the frequency. To analyze the Doherty load modulation network and its impedances Z M and Z P in the frequency domain, the reference plane in Fig. 2 is used as input of a two-port network. The twoport equation in ABCD-parameters yields The transmission parameters for the lossless transmission line TL 0 with Z 0 · ξ as its characteristic impedance are The voltage at the common node V com can be expressed by Inserting (16) into (14), the voltage V M and current I M at the main path input are defined by Rearranging (18) to I M,t and inserting it into (17) yields V M in dependency of the two input currents: Dividing (19) by I M one obtains Z M . According to (13), the ratio of the current amplitudes |I M | and |I P | can now be expressed as For a complex-valued peak-to-main current ratio before transformation α, a phase shift of π/2 at f 0 between I P and I M has to be considered, which is provided by the λ/4 IT at the peak amplifier input: Thus, the Doherty impedance of the main path Z M without saturation can be described by To take the saturation of the main amplifier current source into account, a maximum drain-source voltage V DS,M,max is defined based on I D,M,max and Z M (α t = 0) at f 0 : The behavior considering saturation is conditioned with Finally, the Doherty impedance for the main path with saturation results in Z M,sat is solely real-valued over the frequency and equal to the characteristic impedance of TL 0 . Thus, a maximum broadband matching is reached at this point, which can be defined via ξ. In Fig. 3, these points are highlighted respectively.

Frequency analysis of the load modulation in the peak path
For the peak path, similar considerations can be made. Taking (16) and (18) into account, the peak amplifier Doherty impedance Z P can be derived. Here, the saturation effect for the peak amplifier can be neglected, since the chosen characteristic impedance for TL 1 of R L · N leads to a coherent addition of the currents I M,t and I P . Thus, the highest impedance or voltage magnitude always occurs at f 0 . The saturation of the main amplifier however affects the peak path, which is why a distinction between I M and I M,sat has to be considered for the calculation Z P given by In Fig. 4, the impedance curves for Z P are shown for the same conditions as for Fig. 3. The effect of saturation of the main amplifier is less pronounced for Z P . For input voltages below V in,max /N, Z P approaches infinity. With increasing V in , either the real (ξ = 1) or the imaginary (ξ = 1/N) part of Z P increases. Here, the maximum broadband matching at V in,ξ becomes also evident. The performance for signals with a larger bandwidth depends mostly on the broadband matching properties. However, the ξ-scaled IT is only matched at V in,ξ . Simultaneous matching at back-off and peak level is not achieved. To find the best tradeoff, the impact on the drain efficiency of the ADPA will be examined in the following segment.

Frequency analysis of the drain efficiency
Given the preliminary discussion, an ADPA's DE can be considered. With amplifiers biased in class B, the ratio of RF output power to DC power consumption for Fig. 2 follows: The DE curve with its two efficiency peaks at back-off and maximum output power level is now derived for different frequencies.
For broadband signals, this consideration is necessary to reach a high overall efficiency. As illustrated in Fig. 5, the efficiency trajectories beside f 0 are affected by the frequency-dependent Doherty impedances Z M,sat and Z P . For ξ = 1/N and ξ = 1, they only reach one efficiency peak at V in,ξ . With j = 1/ N √ , V in,ξ is between back-off and maximum input level, so these curves have a local

Drain efficiency depending on probability density function
In order to estimate the broadband efficiency, a PDF-weighted input signal is used. The overall PDF-weighted efficiency DE PDF,B within a bandwidth can be defined as To analyze the previous load modulation networks, a Rayleigh distribution defined by is utilized as an example. With s = 1/N · 2/p √ , the expected value arises at OBO which meets the desired PAPR. As stated in (31), the PDF is considered only for the input voltage, while the distribution is uniform over frequency. Fig. 6 compares DE PDF,B for the three different bandwidths, while ξ is swept. For the used PDF with a PAPR of 8 dB, the highest efficiency is reached at ξ = 0.4, which corresponds to ξ = 1/N. The optimum becomes all the more obvious with increasing bandwidth. Moreover, to ensure maximum efficiency, V in,ξ should meet the expected value. This principle was also found to be true for signals with an uniform PDF. The estimation of the system efficiency should be based on the PDF of the signal to be transmitted and not exclusively on DE curves. This approach should already be considered in the design process.

Design process of the proposed Doherty power amplifier
To prove the theory of section "Analysis of the asymmetric Doherty modulation network with a scaled impedance transformer", an ADPA with three representative values for ξ = (1/N, 1/ N √ , 0.8) is designed. The selected values of ξ result in different characteristic impedances for TL 0 . Thus, further practical effects of the Doherty IT shall be investigated. In this section, the amplifier design procedure, its matching technique, and the implemented input and output matching networks (OMNs) are covered.
The schematic of the proposed circuit is depicted in Fig. 7. A GaN high electron mobility transistor (HEMT) CG2H40010F by Wolfspeed/Cree is used on a Rogers4350 254 μm substrate. Using SMD components instead of λ/4 lines for biasing networks, DC-blocking and input splitter minimizes the required board area yielding a more compact design. According to the fifth generation mobile communications standard (5G), the targeted operation frequency band reaches from 3.4 GHz to 3.8 GHz. The ADPA will be optimized for signals with a PAPR of 8 dB driving a load R L = 50 Ω with its output-related 1 dB compression point at P out,1dB = 42 dBm and the first efficiency peak at P out,OBO = 34 dBm, respectively. According to (10), Z 0 is set to 125 Ω to avoid additional bandwidth limitations by TL 1 . For an OBO of 8 dB, N becomes 2.5 according to (6). Hence, the characteristic impedance of the λ/4 line TL 0 is obtained as follows: 50 Ω for ξ = 1/N, 79.1 Ω for j = 1/ N √ , and 100 Ω for ξ = 0.8.

Optimum load determination with intrinsic node method
Beside the common load-pull method to determine the optimum load for a PA, the current and voltage waveforms at the current source plane of the active device can be used [8]. Since the theoretical considerations of the modulation network are carried out at the current source plane, the parasitics of the package, landing pads, and bias network have to be taken into account for the matching procedure. Fig. 8 illustrates the impedances at different reference planes as well as the two-port blocks transforming the impedances between these planes. Fortunately, the used transistor model allows to simulate current and voltage waveforms of the intrinsic drain node. According to the desired output power and bias conditions, a real-valued load line R OPT,int is applied to its output characteristics.
To determine the optimal intrinsic load for the main amplifier R OPT,M,int and for the peak amplifier R OPT,P,int , the transistors are biased in a deep class AB with V Bias,M/P = −2.9 V. According to the advantages described in [6], an asymmetric drain biasing of V DD,M = 18 V and V DD,P = 28 V is used. The main PA has to at PEP for the specific device and bias conditions. The peak amplifier R OPT,P,int yields at PEP. Based on these values, the impedance at the device/bias plane is varied to identify the optimum external load Z OPT,ext , which transforms to R OPT,int at the intrinsic node. The corresponding impedance characteristics for the main amplifier between OBO and PEP and for the peak amplifier at PEP are shown in Fig. 9. R OPT,int,M and R OPT,int,P are independent of frequency and located on the real axis. Depending on the frequency, they are transformed from the current source plane to the device/bias plane to Z OPT,ext,M and Z OPT,ext,P , respectively.

Output matching network design
The OMN of the main amplifier has to transform the Doherty impedance Z M to the previously determined impedances Z OPT, M,ext . According to (12), this OMN depends on the modulation index α and the scaling factor ξ. To simplify the design procedure and keep the complexity of the OMN moderate, Z OPT,M,ext at the center frequency of 3.6 GHz is used with α = 0 and α = N − 1, respectively. This impedance has to be transformed from Z M (α, ξ) as specified in Table 1.
The OMN is realized as double-cascaded transmission line open-stub design, which avoids the use of lossy SMD components. An optimization algorithm is used to determine the optimal dimensions meeting the upper defined transforming conditions for each value of ξ.
The design of the peak amplifier's OMN, which transforms its Doherty impedance Z P to Z OPT,P,ext , is less complex. The fixed   matching is independent of α and ξ. For the operation below the OBO, the peak amplifier is turned off and should behave as an open circuit at the common node connection. However, this is prevented by the capacitive off-state output impedance of a HEMT. To counteract this, RF shorted-stubs at the landing pad of the drain terminal and the offset line technique [9] were used to push the off-state-impedance of the peak amplifier toward the infinity region. These techniques are a further limiting aspect of an efficient broadband DPA operation due to their frequency dependence. However, the comparability for different values of ξ is maintained due to an identical peak amplifier design. The optimal external impedance at 3.6 GHz is determined with Z OPT,P,ext = (11 − j · 13) Ω. Using (4), this impedance has to be transformed from Z P = 83.3 Ω.

Input matching network design
For the main amplifier's input matching, a tradeoff between high efficiency and gain in the targeted bandwidth was found at an input impedance of (8 − j · 35) Ω with its gate bias set to V Bias,M = −2.9 V. Due to the class C biasing of the peak amplifier with V Bias,P = −4.5 V and a different optimum output impedance, the optimum input impedance is (8 − j · 25) Ω. As shown in Fig. 7, both input matching networks are realized in similar element combinations with minor differences in their dimensions. The 100 Ω resistors in the gate biasing paths ensure unconditional stability.
The λ/4 input delay line in the peak path and the power divider at the input are combined by using the 3 dB hybrid coupler XC3500P-03S by Anaren. It enables a constant 90°phase shift within a bandwidth from 3.3 GHz to 3.85 GHz leading to a more robust performance versus frequency. Moreover, this SMD component is much smaller than an equivalent microstrip line solution.
Large signal simulation for main amplifier Fig. 10 depicts the simulated large signal performance of the designed main amplifiers including their input and output networks. To demonstrate the influence of the load modulation network, it is necessary that the different main amplifiers achieve as equal a performance as possible. Within the targeted frequency range of 3.4 GHz to 3.8 GHz, the operating power gain G P and power-added efficiency (PAE) of ξ = 1/N and j = 1/N √ are almost identical. The main amplifier with ξ = 0.8 has about 0.5 dB less gain at 3.8 GHz but achieves a higher PAE performance at OBO and PEP. Outside the operating frequency, the deviations increase slightly.

Further design aspects
To simulate the design more accurately, a parasitic inductor of 50 pH is added to the simulation test bench at the source node of the transistor. It lowers the gain performance and should be kept as low as possible. To support this, a copper plate with a cavity was manufactured, where the source plate of the transistor is plugged in. In addition, mechanical stability and cooling is provided.
For the input matching network and DC blocking, high-Q multilayer ceramic capacitors GJM0335C1E2R2WB0 (input matching and DC block) and GJM0335C2A4R9BB01 (output DC block) by Murata were used. A small 0201 (0603 metric) package size with low inductive parasitics is required to ensure the operation below self resonance frequency.

Experimental results
For each value of ξ an ADPA was set-up and measured. Fig. 11 shows the test board for j = 1/ N √ . As central measurement instrument, the R&S® ZVA67 network analyzer was calibrated and used for small signal as well as large signal (continuous wave) measurements. To measure the ADPA performance for modulated signals with a certain PAPR, the R&S® SMBV100A signal generator was used.
For the targeted large signal power levels of about 42 dBm with an expected power gain of about 10 dB for a single stage ADPA, an additional driver and attenuator were necessary. The Mini Circuits ZVE-8G was used as pre-driver. This driver has a saturated output power of 33 dBm. Hence, to achieve the desired output power of 42 dBm within this measurement setup, an operation power gain of more than 9 dB would be required.
Due to device-related threshold voltage variations between −3.6 V and −2.4 V, the bias voltage V Bias,M of the main amplifier has to be carefully adjusted to obtain an operating current I D,M = 40 mA [10]. For the peak amplifier, the bias voltage V Bias,P needs to be determined by large signal measurements. This is realized by applying an input power resulting in an output power slightly above the OBO. At this point, a noticeable rise of the peak amplifier's drain current I D,P becomes apparent indicating its activation. By this method the bias voltages V Bias,P are adjusted between −4.3 V and −4.2 V.

Small signal measurements
The scattering parameters of the three ADPAs were measured and compared with the simulated behavior. Since the peak amplifier is biased in class C mode, it is not active for the small signal Table 1. Values for the main amplifier's Doherty impedance Z M with N = 2.5, Z 0 = R L · N, and f = 3.6 GHz measurement. Thus, this measurement mostly reflects the main amplifier performance. Fig. 12 illustrates the forward gain S 21,dB and the input reflection coefficient S 11,dB for the simulated and measured ADPAs. For ξ = 1/N, the measured small signal bandwidth and gain have the highest value. It reaches a maximum gain of 12.3 dB at 3.6 GHz and a 3 dB bandwidth of 700 MHz. The simulated deviation of S 21,dB between ξ = 1/N and ξ = 0.8 is about 0.5 dB. For the measurement, it increases to 1.5 dB. One possible reason is better matching of ξ = 1/N at low input levels, which is also advantageous for process variations. Furthermore, a larger deviation can be observed between 4 GHz and 5 GHz where S 11,dB is higher than −5 dB. The resonance might be caused by the cavity in the copper plate, but it is outside the frequency range of interest.

Large signal measurements
To measure the output power, the PAE and the large signal behavior of the ADPAs, single tone signals were applied. The input power was swept up to 33 dBm for frequencies ranging from 3.0 GHz to 4.2 GHz. The achieved PAE and operating power gain G P performances versus P out at 3.4 GHz, 3.6 GHz, and 3.8 GHz are shown in Fig. 13. The measured results coincide well with the simulation. In terms of G P as well as PAE, the amplifier with ξ = 1/N achieves the best performance. Although advantageous in theory, j = 1/ N √ and ξ = 0.8 do not exhibit the expected broadband matching for output powers above the OBO.
Since the major investigation was done for broadband performance, the measured PAE and G P are plotted over frequency in Fig. 14. Here, three output power levels (34 dBm, 38 dBm, 42 dBm) were selected. For P out = 34 dBm, representing the OBO as well as the V in,ξ of ξ = 1/N, the respective ADPA has the highest PAE over the entire bandwidth. Between 3.4 GHz and 3.8 GHz, a PAE of around 45% was measured for ξ = 1/N. At 3.2 GHz the PAE difference between ξ = 1/N and ξ = 0.8 was around 10%. For P out of 38 dBm, which corresponds to V in,ξ for j = 1/ N √ , the ADPA with ξ = 1/N still has the highest PAE. Especially in the frequency range from 3.1 GHz to 3.7 GHz, a constant difference of about 9% compared to ξ = 0.8 can be observed. For the PEP output power of 42 dBm, the PAE curves of ξ = 1/N and j = 1/ N √ are very similar and range from 57%   to 63% in the frequency band between 3.5 GHz and 4.0 GHz. The ADPA with ξ = 0.8 achieves P out = 42 dBm only between 3.7 GHz and 3.8 GHz. Within this 200 MHz bandwidth, it even has 5% less PAE of 58%. For frequencies that are not within this range, its G P drops below 9 dB. Hence, an output power of 42 dBm could not be measured here. Table 2 compares the measured large signal performance of the three measured ADPAs. Since the stand-alone main PAs operate similarly, the performance difference of the ADPAs results from the ξ-dependent modulation network. Compared to ξ = 0.8, ξ = 1/N and j = 1/ N √ achieve a larger bandwidth, higher gain and PAE. Overall, ξ = 1/N has the best performance.
Possible reasons for the disagreement between the theory of section "Analysis of the asymmetric Doherty modulation network with a scaled impedance transformer" and the measurement results are losses of gain and bandwidth in the OMNs and impedance mismatch caused by process variations. Based on the Doherty impedance for the main amplifier Z M mentioned in Table 1, an impedance transformation ratio of 12.3 (α = 0) and 2 (α = N − 1) for ξ = 0.8 is needed. For ξ = 1/N, the impedance transformation ratio is 6.2 (α = 0) and about 1 (α = N − 1), which makes it more robust against process deviations and model inaccuracies. A similar design on a thicker substrate (e.g. 512 μm) or different ϵ r is suggested here to realize microstrip lines with higher characteristic impedances by wider, less process sensitive conductor paths.

Power-added efficiency in dependency of the probability density function
To benchmark the ADPAs, the averaging method with PDF weighting is used, as it was demonstrated in section "Drain efficiency depending on probability density function". Now the PAE is used instead of the DE as averaged value, which includes the gain performance of each amplifier. To compare all three ADPAs, the peak output power is lowered by 1 dB to 41 dBm with an observed bandwidth of 400 MHz reaching from 3.4 GHz to 3.8 GHz. This corresponds to a relative bandwidth of 11%. By lowering the peak output power by 2 dB to 40 dBm, a broader bandwidth of 900 MHz (3.2 GHz to4.1 GHz) can be used. Hence, the calculation of the averaged PAE is done for a fractional bandwidth of 25%. The results are shown in Table 3 with the highest PAE PDF,B for ξ = 1/N for both cases.
Using the initially specified peak output power P out,peak = 42 dBm within a 400 MHz bandwidth from 3.5 GHz to 3.9 GHz a PAE PDF,B of 38.8% for ξ = 1/N can be achieved.

Power-added efficiency with modulated signals
In order to gain a more operation-related performance, comparison of the ADPAs measurements with modulated signals was carried out. The utilized baseband signal with a bandwidth of 50 MHz, a 256QAM modulation scheme and an EUTRA/LTE  baseband filter leads to a PAPR of 7.9 dB. These baseband specification was chosen as example for a 5G signal transmission scenario. The PAE was measured for carrier frequencies swept from 3.425 GHz to 3.775 GHz, while keeping the average output level around 32.5 dBm. The measurement results are shown in Fig. 15. Here it becomes evident that the ADPA with ξ = 1/N achieves the highest PAE for carrier frequencies higher than 3.7 GHz. Furthermore, this ADPA version has the highest PAE performance of 41%, as averaged over the measured frequency range. The ADPAs with j = 1/ N √ and ξ = 0.8 reach a slightly lower averaged PAE of 40% and 39%, respectively. These results also confirm the trend calculated in the previous subsection "Power-added efficiency in dependency of the probability density function".

Conclusion
To classify the achieved performance, the circuit is compared with similar publications in Table 4. For this purpose, symmetric and asymmetric architectures with enhanced fractional bandwidth (BW) are considered.
To the authors' knowledge, no similar work has been published that investigates the broadband effect of the main amplifier's IT for an ADPA. The considerations in section "Analysis of the asymmetric Doherty modulation network with a scaled impedance transformer" extend the existing state-of-the-art theory on ADPAs and provide an enhanced approach for a more energy-efficient circuit design.
A major field of application for DPAs are massive MIMO base stations for latest and future mobile standard communications. Due to the large number of devices and limited space in such base stations, the occupied board area is of great importance. In this work, the by far most compact amplifier design was demonstrated. The achieved board area is smaller by a factor of 2.3 compared to the next smallest design. The use of a discrete hybrid coupler at the input as well as the avoidance of long microstrip lines have proven to be very beneficial.
For the purpose of this comparison we focused on the amplifier with ξ = 1/N, since it has the best performance. The obtained PAE peak of 52.0% to 63.0% at peak power is roughly the same as in [4,[11][12][13]. However, those circuits are operating at lower frequencies. The study in [4] uses the same active component, but is designed for a higher output power and utilizes a higher drain voltage. This is beneficial for an efficient operation due to a lower impact of the knee voltage. For an ADPA with an OBO larger than 6 dB and a center frequency higher than 3.0 GHz, the highest PAE performance is achieved with this work. To reach such a high PAE, sufficient operating gain has to be ensured. In this work, we demonstrated the highest value of 8.2 dB to11.6 dB for center frequencies above 2 GHz.
The comparison with the state-of-the-art emphasizes that the proposed design approach is a suitable solution for efficient broadband power amplifiers with a high dynamic range. The intrinsic node matching turns out to be a promising method to ensure an efficient PA design. The maximum broadband matching at V in,ξ can be applied for transistors with different output impedance or for different values of Z 0 with an additional post matching network in the future. However, to meet an efficiency optimized operation for signals with high PAPR and instantaneous bandwidth, matching at the expected value is beneficial.