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Microprocessor Architecture
From Simple Pipelines to Chip Multiprocessors


  • Date Published: February 2010
  • availability: Available
  • format: Hardback
  • isbn: 9780521769921

£ 65.99

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About the Authors
  • This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers • Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

    • Describes how components of a microprocessor work at a black box and algorithmic level often using pseudo-code
    • Has current and historical examples drawn from commercial systems (in side-bars) and research projects
    • Consistently presents topics from conceptual ideas to alternate ways of implementation providing performance metrics whenever possible
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    Reviews & endorsements

    'The book gives a comprehensive and profound description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalers … The book is very well structured with good presentation of the material. Each chapter finishes with many exercises, examples and additional literature. All the references are very up-to-date. As a conclusion I warmly recommend this book as a textbook for a course or just as a reference book.' Zentralblatt MATH

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    Product details

    • Date Published: February 2010
    • format: Hardback
    • isbn: 9780521769921
    • length: 382 pages
    • dimensions: 257 x 180 x 25 mm
    • weight: 0.84kg
    • contains: 104 b/w illus. 20 tables 117 exercises
    • availability: Available
  • Table of Contents

    1. Introduction
    2. The basics
    3. Superscalar processors
    4. Front-end: branch prediction, instruction fetching, and register renaming
    5. Back-end: instruction scheduling, memory access instructions, and clusters
    6. The cache hierarchy
    7. Multiprocessors
    8. Multithreading and (chip) multiprocessors
    9. Current limitations and future challenges.

  • Resources for

    Microprocessor Architecture

    Jean-Loup Baer

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  • Instructors have used or reviewed this title for the following courses

    • Computer Architecture lll
    • Computer Design
    • Computer Systems Architecture
    • Microprocessor Architecture
  • Author

    Jean-Loup Baer, University of Washington
    Jean-Loup Baer is Professor Emeritus of Computer Science and Engineering at the University of Washington, where he has been since 1969. Professor Baer is the author of Computer Systems Architecture and more than 100 refereed papers. He is a Guggenheim Fellow, an ACM Fellow, and an IEEE Fellow. Baer has held several editorial positions, including editor-in-chief of the Journal of VLSI and Computer Systems and editor of the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the Journal of Parallel and Distributed Computing. He has served as General Chair and Program Chair of several conferences, including ISCA and HPCA.

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