Design of CMOS Phase-Locked Loops From Circuit Level to Architecture Level
- Textbook
Description
Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to…
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Key features
- Introduces key theoretical concepts in their simplest form and builds them up to encompass more complex systems
- Offers methodical coverage of modern CMOS phase-locked loops (PLLs) from transistor-level design to architecture development
- Demonstrates how unsuccessful design efforts can be revised to reach new, more practical solutions
- Based on the author's twenty years of teaching CMOS PLL design
About the book
- DOI https://doi.org/10.1017/9781108626200
- Subjects Circuits and Systems,Engineering
- Format: Hardback
- Publication date: 12 March 2020
- ISBN: 9781108494540
- Dimensions (mm): 253 x 203 mm
- Weight: 1.37kg
- Page extent: 506 pages
- Availability: Available
- Format: Digital
- Publication date: 05 February 2020
- ISBN: 9781108626200
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