Hostname: page-component-848d4c4894-p2v8j Total loading time: 0 Render date: 2024-04-30T14:59:40.666Z Has data issue: false hasContentIssue false

n-wells voltage contrast imaging with a Focused Ion Beam

Published online by Cambridge University Press:  01 February 2011

Erwan Le Roy
Affiliation:
NPTest, Inc, 150 Baytech Drive, San Jose, CA 95134, USA
Mark Thompson
Affiliation:
NPTest, Inc, 150 Baytech Drive, San Jose, CA 95134, USA
Get access

Extract

Using a focused ion beam (FIB), secondary electron (SE) imaging of n-wells under oxide from the backside of thinned integrated circuits without electrical bias was accomplished. From the backside, the n-wells were initially observed at a remaining silicon thickness ∼4.5μm, which correlates to the actual implant depth where n and p carrier concentrations are equal. When the wells were FIB imaged, contrast appeared dark relative to the p substrate. During deposition of the oxide film, the n-well brightness changed from dark relative to the p-substrate, to bright. It appears that initially during this deposition step the interaction volume of the beam reached the silicon/oxide interface to create tunneling electrons. This phenomenon dominated the capacitive effect. Then as the film thickness increased the capacitive effect prevailed. The imaging structure is analogous to a Metal-Oxide-Semiconductor (MOS) capacitor. The n- and p-MOS capacitive properties yielded a permanent imaging contrast. At an optimized oxide thickness (130nm), the n-wells appear white relative to the p-substrate with a contrast up to 85% {(Ip-substrate − In-wells)/(Ipsubstrate + In-wells)}.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Sealy, C.P., Castell, M.R, Wilshaw, P.R, Jap. Soc. E. Microscopy. 49(2), 311 (2000).Google Scholar
2. Suthar, S. C., Hack, P., Sarwar, N., Martinez, M., U.S. Patent No. 0153192A1 (Aug. 2003)Google Scholar
3. Laszlo, Voros, CMOS baseline process in the UCB microfab. Lab. (2003).Google Scholar
4. Howie, A., J. Microscopy. 180, 192 (1995).Google Scholar
5. Elliott, S.L., Broom, R.F., Humphreys, C.J., Inst. Phys. Conf. Ser. No 169 (2001); J. Applied. Phys. 91, 9116 (2002).Google Scholar
6. Janssen, A.P., Akhter, P., Harland, C.J., Venables, J.A., Surf. Sci. 93, 453 (1980).Google Scholar
7. Cole, E.I. Jr in Micro. Failure. Analysis Desk Reference, edited by EDFAS pp. 133.Google Scholar
8. Goetzberger, A., Bell syst. Tech. J. 45, 1097 (1966).Google Scholar
9. Nicollian, Brews, in MOS Physics and Technology, pp. 80 (2003).Google Scholar