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Ultra-Shallow Junction Formation Technology from the 130 to the 45 nm node

Published online by Cambridge University Press:  17 March 2011

Amitabh Jain
Amitabh Jain*
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas 75243, U.S.A.
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Abstract

One of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer Ultra-High Temperature anneals must be considered.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 810: Symposium C – Silicon Front-End Junction Formation-Physics and Technology , 2004 , C5.6
Copyright
Copyright © Materials Research Society 2004

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