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Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy

Published online by Cambridge University Press:  17 March 2011

M. Wimplinger
Affiliation:
EV Group, E. Thallner Str. 1, 4780 Schaerding, Austria
J.-Q. Lu
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180, luj@rpi.edu
J. Yu
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
Y. Kwon
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
T. Matthias
Affiliation:
EV Group Inc., 3701, E. UniversityDr., Phoenix, AZ 85034, m.wimplinger@EVGroup.com
T.S. Cale
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
R.J. Gutmann
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
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Abstract

Wafer-level three-dimensional (3D) integration as an emerging architecture for future chips offers high interconnect performance by reducing delays of global interconnects and high functionality with heterogeneous integration of materials, devices, and signals. Various 3D technology platforms have been investigated, with different combinations of alternative alignment, bonding, thinning and inter-wafer interconnection technologies. Precise alignment on the wafer level is one of the key challenges affecting the performance of the 3D interconnects. After a brief overview of the wafer-level 3D technology platforms, this paper focuses on waferto-wafer alignment fundamentals. Various alignment methods are reviewed. A higher emphasis lies on the analysis of the alignment accuracy. In addition to the alignment accuracy achieved prior to bonding, the impacts of wafer bonding and subsequent wafer thinning will be discussed.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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