The OFF current in a-Si TFTs is an important parameter, especially for applications such as active matrix liquid crystal displays. In some demanding applications operation at 70°C or higher is required. This paper reports studies of the OFF current limiting mechanisms at room temperature and above. It is shown that the limiting mechanisms are hole injection from the drain junction at room temperature and electron conduction at higher temperatures. The importance of silicon thickness and interface state density at the passivation interface is stressed.