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Improved off-Characteristics of a-Si Vertical-Type Mosfets

Published online by Cambridge University Press:  26 February 2011

Hiroyuki Okada ,
Jun'ichi Sakano ,
Shunri Oda  and
Masakiyo Matsumura
Hiroyuki Okada
Affiliation:
Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo 152, Japan
Jun'ichi Sakano
Affiliation:
Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo 152, Japan
Shunri Oda
Affiliation:
Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo 152, Japan
Masakiyo Matsumura
Affiliation:
Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo 152, Japan
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Abstract

We propose a new structure of vertical a-Si FET with the intermediate layer between the source and drain consisting of the multi-layer structure. The mechanism of off-current in short-channel vertical-type a-Si FET is discussed. The multilayered structure is incorporated in an attempt to reduce the back gate effect. The preliminary experimental results are also presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 118: Symposium E – Amorphous Silicon Technology , 1988 , 219
Copyright
Copyright © Materials Research Society 1988

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