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Metallic Impurities in n- and p- Type Silicon: Dlts Studies

Published online by Cambridge University Press:  03 September 2012

Aditya Agarwal
Affiliation:
North Carolina State University, Department of Materials Science and Engineering, Raleigh NC 27695–7916
Z. J. Radzimski
Affiliation:
North Carolina State University, Department of Materials Science and Engineering, Raleigh NC 27695–7916
A. Buczkowski
Affiliation:
North Carolina State University, Department of Materials Science and Engineering, Raleigh NC 27695–7916
F. Shimura
Affiliation:
North Carolina State University, Department of Materials Science and Engineering, Raleigh NC 27695–7916
G. A. Rozgonyi
Affiliation:
North Carolina State University, Department of Materials Science and Engineering, Raleigh NC 27695–7916
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Abstract

Deep level majority and minority carrier traps in p+/n and n+/p junction diodes have been investigated. The junctions were fabricated on n- and p- type silicon which was intentionally and uniformly doped with heavy metals Cr, Fe, Ni, and Au during Czochralski crystal growth. The activation energies of the traps in these devices has been determined using a computer based Deep Level Transient Spectroscopy system which stores and analyzes entire capacitance-time transients. The capacitance-time data sets have been analyzed using the standard rate-window method as well as by a new algorithm which is able to test for the existence of a single exponential. The new algorithm has shown that only one of the ten traps measured contained a single exponential. Rate-window analysis of all the data sets, however, yielded energy levels based on the expectation of a single-exponential, despite the inherent non-exponentiality of the transients. Implications on the reliability of results obtained by the rate window method have been discussed. Possible reasons for the observed non-exponentiality in the data have been suggested based on a study of simulated data.

Type
Research Article
Copyright
Copyright © Materials Research Society 1992

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References

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